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LP87702-Q1: Schematic review

Part Number: LP87702-Q1

Hi Team,

There is a good new that we DIN LP87702DRHBRQ1

And there have one thing need your support!
1.Please help check this SCH, THX

2.In addition, customer currently reports that Power-Good (PG0) on LP87702-Q1 doesn’t happen! 

Below yellow is Power-Good (PG0) waveform

  • Hi Kygo,

    PG0 monitors only the voltage levels of BUCK0, BUCK1 and input voltage. I can't quite read what is the timescale in the scopeshot but the PG0 rise is delayed by 11 ms so it may not be visible in the scopeshot. Powergoods in LP87702D-Q1 have 11 ms delay once the monitored voltages have reached the correct levels (PGx_RISE_DELAY bit).

    • Could the customer try to measure buck output voltages and input voltage and see if they are within the required monitoring thresholds (+-90 mV for bucks and +-10% for VANA)?
      • 1.2 V seems to be around 1 V in the scopeshot
    • Is R168 populated?
    • If possible could they try to read BUCK_STATUS register (address 0x26) and DIAG_STATUS (address 0x28) to see what is the status of the bucks and VANA).

    Comments on the schematic:

    • Check that R170 is populated if nINT is used.
    • Make sure C62 is placed directly between VANA and AGND pins.
    • Make sure R87 is populated unless there is a pullup somewhere else. WD_RESET is open drain and requires a pullup resistor.

    Best regards,

    Samuli Piispanen

  • Hi Samuli,

    updated, and now both PG1 and PG0 cannot be Active High

    1.Could the customer try to measure buck output voltages and input voltage and see if they are within the required monitoring thresholds (+-90 mV for bucks and +-10% for VANA)?

    2. 1.2 V seems to be around 1 V in the scopeshot

    >>>LP87702K-Q1

    3.Is R168 populated?

    >>>not connected

    4.If possible could you try to read BUCK_STATUS register (address 0x26) and DIAG_STATUS (address 0x28) to see what is the status of the bucks and VANA).

    >>>Do we need to use the EVM Tool to read it? Or is there a suggested tool?

    5. Check that R170 is populated if nINT is used. >>>YES

    Make sure C62 is placed directly between VANA and AGND pins.>>>YES

    Make sure R87 is populated unless there is a pullup somewhere else. WD_RESET is open drain and requires a pullup resistor.>>>YES

     

  • Hi Kygo,

    >>>LP87702K-Q1

    Do you mean that you are using LP87702K-Q1 and not LP87702D-Q1 as shown in the schematic? VMON1 must be 1.2V for LP87702K-Q1 instead of 0.65V. The voltage divider connected to VMON1 pin will cause both PGOODs to stay low unless the divider has been removed.

    Best regards,

    Samuli Piispanen

  • Hi Samuli,

    Currently there is already could get  PG0_RISE_DELAY=11ms !


    But PG1 is still not Active high! Is it possible that cause R168 is not connected to any resistor?

  • Hi Kygo,

    I just wanted to let you know that Samuli should be able to reply to your latest response sometime tomorrow. Thank you.

    Regards,

    Alex

  • Hi Alex

    Thanks for your hard work!

  • Hi Kygo,

    Is the device LP87702K-Q1 and now the PG0 is OK but PG1 is not getting active? If the device is LP87702K-Q1 could you please provide me the updated the schematics.

    But PG1 is still not Active high! Is it possible that cause R168 is not connected to any resistor?

    R168 should not be needed. PG1 requires a pullup resistor though so R122 is mandatory. Is R69 populated?

    Only difference between PG1 and PG0 in LP87702K-Q1 is that PG1 also monitors buck outputs. Therefore, please measure the output voltages of the bucks with a multimeter to get an accurate reading of the DC levels.

    Best regards,

    Samuli Piispanen

  • Hi Samuli

    Is the device LP87702K-Q1 and now the PG0 is OK but PG1 is not getting active?

    >>> Yes

    If the device is LP87702K-Q1 could you please provide me the updated the schematics.

    >>> May I share schematic with you offline? THX

  • Hi Kygo,

    Let's continue this via emails.

    Best regards,

    Samuli Piispanen