TPS544C20: Layout

Hi Ryota

     The AGNDSNS needs to be Kelvin connected to AGND. To do that you need to drop vias and take it in another layer as the top layer has the thermal pad and you will not have space to route the AGNDSNS trace. Also, Thermal pad will carry the noise power stage return current. So it is better to route it in another layer than close to the thermal pad to avoid noise issues.

As the datasheet recommends, Kelvin connect AGNDSNS on another layer.

The return current will find the path of least impedance and returning to the IC using the GND pins is the shortest. Some amount of current will still flow through Thermal pad. It is hard to quantify.

Regards,

Gerold

Please see layout example in datasheet.

Ryota Shibahara said:

・Why the AGNDSNS should be on another layer?

the AGNDSNS to AGND connection is recommended to be on a separate layer for routing distance restrictions since these pins are on opposite ends of the IC and there are many IC pins that require routing and fan-out between them.  Routing AGNDSNS to AGND between the thermal pad (GND) and Pins 1 through 12 on the top layer might be possible, but the Exposed pad and IC pins are so closely spaced that such a configuration would force the AGND to AGNDSNS connection to be too narrow to effectively transport the required current.

Ryota Shibahara said:

・If AGNDSNS and the thermal pad are the same layer (surface layer) with a gap of 0.14 mm(0.00551 inches), is there a possibility of noise malfunction?

AGNDSNS and the exposed pad will be in close proximity on the top layer, and that is not a problem.  AGNDSNS is internally connected to the exposed thermal pad with a very low impedance connection.  What is critical for proper function is that there is no connection between the Exposed Pad (GND), Power Ground (PGND) and the AGNDSNS to AGND connection externally to the IC so that the AGNDSNS pin provides a kelvin sense of GND voltage at this internal connection and not some external connection point.

Ryota Shibahara said:

　Is there actually such a case? Can the case be an OVW/OVF/OCF false positive? What is the mechanism?

Internally to the IC, the current is sensed by the differential voltage between the AGND pin and the SW pins.  When AGND is connected to AGNDSNS, the current sense senses the resistance between the internal GND kelvin connection and the internal SW kelvin connection, providing the most consistent and accurate sense resistance. 

The resistance between these two points is approximately 2mΩ.  If the AGND to AGNDSNS connection is shorted to GND or PGND at some other point on the PCB and AGND is kelvin sensed to a point on the PCB instead of the internal connection to GND provided by the AGNDSNS pin, the sense resistance will include PCB trace and solder resistance.  Every 20μΩ of resistance will add 1% to the sensed current and reduce the current limit thresholds by 1%. 

Experimentally, we have seen this add 10-15%.

Additionally, there are currents that flow between the AGND pin and the GND net during normal IC operation.  These current require a low inductance, low resistance path to avoid introducing additional drop between the AGNDSNS kelvin ground sense and the AGND pin.  if the trace from AGNDSNS to AGND is not both short and wide, these currents will introduce additional drop between AGND and AGNDSNS, and every 2mV of drop will be sensed as an additional ampere of current.

Ryota Shibahara said:

・Is the return current flowed to the thermal pad as much as GND (PGND)?

The ratio of current flow between the Exposed Pad and pins 13-20 depends heavily on external routing factors.  Their internal connection is approximately 3mm wide with thickness of approximately 5oz copper.  On boards with more than 5oz of ground routing and planes, the majority of ground return currents from the power stage are flowing vertically in the thermal pad to the PCB.  On boards with less than 5oz of ground routing and planes, the majority of ground return currents from the power stage are flowing laterally from pins 13-20.