Hi Team,
in datasheet figure 25, when it enter into current limit, there seems a delay that current goes higher. is it designed for that ? Thanks.
BTW, have we met issue that it wrong trigger OCP when Vin has spike? Thanks.
BRs
Given
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Hi Team,
in datasheet figure 25, when it enter into current limit, there seems a delay that current goes higher. is it designed for that ? Thanks.
BTW, have we met issue that it wrong trigger OCP when Vin has spike? Thanks.
BRs
Given
Hi Given,
Thanks for reaching out to us. We will get back to you tomorrow.
Hi Given,
Please see the responses in the order of your queries.
1) This is due to CISS of the MOSFET. The GATE will take some time (hundreds of μs) to come down to a level to regulate it so that the current flowing through the load is getting limited at ICL1.
2) This can happen in Hot Swap controllers. Please see this app note for more details.