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TPS6521855: Please check if it's suitable for DDR4 solution application

Jack Cha
Mastermind 8154 points
Part Number: TPS6521855
Other Parts Discussed in Thread: TPS65218, TPS51206, TPS6521815

Hi TI.

There's a question that customer wants to clarify.

TPS6521855 is used for SK-AM64 EVM as below.

Is it possible to use TPS6521855 with DDR4 instead of LPDDR4? 

Customer considers to use DDR4 due to performance issue if DDR4 has better performance.

If it's not sufficient for DDR4, What could be recommended for DDR4 design.

Thanks.

  • 0
    TI__Mastermind 19976 points

    Hi Jack,

    Thanks for reaching out! The TPS6521855 comes pre-programmed to support the voltages required by LPDDR4. Customers can use the two PMIC solution with DDR4 but they would have to re-program the DCDC1 voltage on the TPS65218x PMIC from 1.1V to 1.2V. This can be done with TPS6521815 which comes with a blank EEPROM for customers to program it and match the application requirements. For prototype, they can re-program the TPS6521815 PMIC using the Programming BoosterPack before soldering the device in their board. For production, they will most likely have to work with Arrow (TI approved distributors) for the programming services to order TPS65218x PMICs with a custom config that would reflect most of the TPS6521855 configurations with the exception of the DCDC1 output voltage. For the other voltages, the 2.5V coming from DCDC4 on the TPS65218 PMIC can be used to supply VPP and a discrete like TPS51206 can be used for VTT. 

    Even though the two PMIC solution has its advantages because of the amount of rails available to support multiple peripherals, I also wanted to highlight our single PMIC solution for AM64x processor and DDR4 memory. This is the most optimized power solution for this processor due to several advantages including cost, size, better thermal performance and block diagrams are available to support both DDR4 as well as LPDDR4. Additionally it was extensively tested in the lab for power, sequencing, brownout, and fault conditions. You can find more information in the following link: https://www.ti.com/lit/an/slvaes0/slvaes0.pdf

    Thanks,

    Brenda