Hi,
I believe I have finally worked out why the CFET and DFET faults were occurring.
The maximum voltage across the sense resistor is +/-100mV
The ADC quantisation voltage is hence 100mV / 2^16 = 1.5uV
For the recommended 1mR sense resistor, this represents quantisation current of 1.5mA
Under these conditions, the default 5mA threshold is almost 5 times larger than the quantisation current, offering significant margin for noise, etc.
As our application uses a 0.25mR sense resistor, the quantisation current is 6.1mA, meaning that any drift or noise greater than 1LSB is sufficient to trigger the fault if it is sustained for 5 seconds.
Interestingly, we have only observed trigger of this fault in around 10% of our packs, but do plan to increase our margin to an equivalent factor of at least 5-fold.
I'd appreciate it if someone could review this - does it appear to be sound reasoning?
Thank you,
Jeremy.
