BQ77915: Design Review

Hello Samruddhi,

There are a few points that I wanted to comment on regarding your schematic.

For the top stack BQ77915 IC: 

• The CHG/DSG to CTRC/CTRD resistances should be 10-MΩ for the top devices.
• OCDP should be 10-MΩ for the top and middle device. This is mentioned in Section 9.3.2.6 of the datasheet. Only the bottom device should be 750-kΩ for the intended OCD delays.
• R42/R41 doesn't seem like they are needed. You could directly connect them to GND2. I don't believe it would cause any issues to leave connected, but it could save you a couple of components on the board.
• You must add a diode on the LD pin as shown in the Stacking Implementations with bq77915 application report and as mentioned in Figure 10-3 and Figure 10-7 of the datasheet.
• The VTB/TS connections worries me a little, it seems from the layout that you intended to connect the thermistor between these. TS and VTS (through the 10-kΩ) should connect together to one side of the thermistor, the other side should connect to GND2. As seen in the stacking application report.

For the middle BQ77915 IC:

• Resistors to CTRC/CTRD seem correct here.
• OCDP should be 10-MΩ.
• Also add the diode on the LD pin as explained above.
• Same concerns regarding VTB/TS connection.

For bottom stack BQ77915 IC:

• Seems correct.
• Diode on LD pin is optional. See notes in the datasheet. 
• Same concerns regarding VTB/TS connection.
• OCDP is correct here.

For external cell balancing and cell input connections:

• This is optional. I see your FET gate-source absolute max is 20-V, so this next recommendation may not be needed. But it may be a good way to make sure nothing gets damaged during short-circuit.
  • A 10-kΩ gate resistance and a Zener diode at the gate-source may be desirable to protect the external FETs from events of heavy load, like a short circuit. Albeit for a different part (but similar), Section 4 Cell Balance of the bq769x0 Family Top 10 Design Considerations application report may be helpful to understand this. 
• I am a bit confused as to how the ground connections work. For the top stack, GND2 should be connecting to CELL 10 of the middle device, and GND1 should be connecting to CELL 5. I notice these are connected to a CELL0_GNDx. Make sure they are connected on the appropriate grounds of the bottom devices.

For the CHG/DSG FETs:

• I see you may be following the bq77905 Using Multiple FETs application report. This is good.
• Only thing I can point out, is that you may want to lower the DSG pin 5.1-kΩ resistance to make the switching speed of FETs faster. The bq77905 Multiple FET application report uses a 2.2-kΩ resistance. You can choose this based on your desired rise/fall time of the FETs.
• Sense resistor connection seems good.

I hope this was helpful :).

Best Regards,

Luis Hernandez Salomon

Hello Samruddhi,

Which diode should be selected for this? Power diode? what ratings?
The LD pin is internally clamped to 20-V (V_LDCLAMP in the datasheet). The diode is to protect the pin from very negative voltages (e.g. - 30-V), choose a diode that is able to block expected negative voltages. 

For this AFE I followed the datasheet. Other AFEs design I have gate resistors for balance FETs. Working point of view I would like to understand how same pin of AFE acting as a cell voltage input & balance control for AFE?
I am not sure if I understand the question here. I am assuming you are asking how can the same pin be used for cell measurement and cell balancing. For this, it may be helpful to see Section 9.2 Functional Block Diagram of the datasheet. Cells are balanced through an internal FET that is turned on and off during cell balance. While it is off, the IC will measure the cell voltage and check its state. I would also recommend you read Section 9.3.4 Cell Balancing of the datasheet.

Can you please explain how to select the DSG pin resistor & Gate resistor as per MOSFETs rise/fall time & continuous current.
This is something you'd be expected to determine. We provide some rise/fall data in Section 8.5 Electrical Characteristics — CHARGE AND DISCHARGE FET DRIVERS of the datasheet. The rise/fall time of your FETs would depend on the gate capacitances and gate resistances. For multiple FETs you'd want a slightly lower resistance for faster switching. Careful, you do not want a too low resistance as it could create parasitic oscillations between the FETs and could lead to large voltage transients during short-circuit events, but too high and it could slow down the switching too much. This is something you may have to test and figure out. For a single FET, 5.1-kOhm is okay, for multiple FETs, we used 2.2-kOhm in our designs.

How to implement the load & charger detect in any BMS using op-amp(any other component) if AFE doesn't have that functionality?
Load detect in the BQ77915 is only really used as a way to recover from certain faults. Different AFEs will have different ways to recover from certain fault conditions, none really have a charger detect. The way the IC "detects" these, is through the current through the sense resistor. Usually the FETs are ON, allowing current flow unless there is a fault condition. However, I believe your idea could work if you desire to have a way to detect and display the charger/load on parts that do not explicitly measure the current/voltages. If your part is able to measure the current or voltage of the sense resistor, you would be able to conclude if the device has a charger or load inserted (or none at all).

Best Regards,

Luis Hernandez Salomon