TPS2491 - Current step in Figure 12 of Datasheet

Please look at the SOA curve for the FET. It looks like your start point 15V across the FET and 10A is between the 1 and 10mS range. Given there is not much margin here and the SOA should be derated for ambient greater than 25C, you should lower the power limit a little. There is some room to lower VPROG (0.667V).

Thanks Bob,

Perhaps I'm not interpreting the power limit correctly.  We are trying to charge 2.2mF of capacitance.  At 5A this works out to 6ms of charge time.  

How can I set the power limit to regulate the current to 5A during startup while allowing the steady state condition to pass ~12Amps that my application calls for?

I'm trying to avoid forcing the device into false-retry.

Thanks,

If a series rc is put on the gate of the mosfet to GND, the FET output will turn on following the gate instead of a power limit start. As you noted, the slope determines the current. If the 6mS is 5A output to charge the capacitor, the gate capacitor (C = (I x V ) / T) = 10nF. A 1K resistor is recommended. This has some minor mention in the datasheet. It doesn't trip or current limit at 5A but the current shouldn't go above 5A on start.

I interpreted the original question with respect to the initial "step" or rise time of the current in Figure 12.

Thus, the RC circuit added to the gate drive signal would not only change the behaviour of the initial step (original question) but then the waveshape following would be drastically different.

I think the capacitor that the datasheet refers to affect this initial "step" or rise of the current in Figure 12 is a different one....    I would check the datasheet to find that particular node where the capacitor is added.

This thread has the time-frame for the whole turn-on response for the MOSFET and associated hotswap control IC, so perhaps my interpretation is not correlating with the orginal author's question....

A bit late for this response, but my thoughts....

As a follow-up, I looked this up on the datasheet and it is the PROG pin (node) that one may add a capacitance to which will then affect the initial "step" or ramp of current.

Also in the last reply the equation for the value of 10 nF of capacitance was given as:  C = (I * V) / T.

Yet a value of 10 nF was stated as a result, with no values given for each parameter.

Since the gate capacitance is in a different part of the circuit, as compared to the calculations for charging the 2mF of capacitance with 5A for 6msec, the values for I and V are related to the gate drive signal.

I can assume that the time (T) is related to the aforementioned 6 milliseconds for the time it takes to charge up the output of the MOSFET switch element.

Looking at the datasheet for parameter values to assume for I and V, there is a gate sourcing current in the electrical tables and voltage from gate to output....

Let's work with the current first...

Current (I) may be a min value of 15 uA (microAmps), a nominal value of 22 uA (microAmps), and a max value of 35 uA (microAmps).

Assumption:  use 35 uA.

Voltage (V) is listed as the voltage from gate to output with a minimum of 12 volts and a maximum of 16 volts.

But....

The capacitor in question for this RC gate signal is connected to return (ground), and not the source.

Therefore, this capacitor will see this gate drive voltage signal only with respect to return (ground).

Earlier in this thread, the output was assumed to be very close to the input voltage (15 volts).

This is the voltage that the gate drive signal will be superimposed (riding on top of) upon.

Assumption:  15 + gate-to-source voltage = 15 + 12 (minimum) and 15 + 16 (maximum).  Use 31 volts.  (Perhaps consider 15 + 7 = 21 volts?)

Now let's do the math:  C = (V*I)/T = (31 volts * 35 uA) / (6 milli-seconds) = 180 mF (milli-Farads)????

Must have an error in the assumptions for the values of voltage and current?

Try the "consideration" of 21 volts:  (21 volts * 35 uA) / 6 milli-seconds) = 122 mF (milli-Farads)?? 

The major problem here is the micro-amps being divided by milli-seconds NOT yielding a value in nanoFarads.....  (10 nF in this specific case)..

Let me see if I can help a little.

The original question revolves around whether the initial 10A current during inrush is counter to basic hotswap.  While this may depend on your point of view, in general this is OK for a hotswap.  Some basic requirements are that a unit should plug-in without drawing uncontrolled current (perferable no current - but sometimes a small cap is OK),  and that the source should not be overloaded during charge of the downstream capacitors (inrush).  In addition, many people add functionality of overload (fault) protection and some other features (e.g. on/off switch).  Another way to think of this is that if full-load current is 12A, protection is 15A or more, then is there really a difference between drawing 5A and 10A as the first current.  Note that the internal delay keeps the part from drawing power immediately.

So - this would be OK given a better MOSFET choice for the application.  While the selected IR device ( IRFS3206) is a perfectly acceptable device as a switch, the dramatic derating in the lower-right corner of the SOA curve indicates it is not that good a choice for operation in the linear region for significant time.  Normally the SOA curves are constant heating curves (in this case 25C to 175C), however if you look at the P*T along the 10ms curve, you find it much lower at Vds > 10V.  The internal parasitic bipolar transistor is taking over operation in this region, and it is much more susceptible to hotspotting and failure than the intended MOSFET structure.  Normally, you can derate the SOA curves based on the desired delta-Tj, however in this case it is problematic.  So,  a choice of a stronger MOSFET in this region would be a good thing.  The EVM for the TPS2492 (uses same basic limiting engine) uses TI's CSD16401Q5A as a pass device as an example (solutions are not specific to our MOSFETs) of a device with good SOA for the application.

If you decide that you don't like the 10A, you can reduce the leading edge by forcing the power dissipation number down to say 60W (12V x 5A).  Be carefup to not reduce the IxV corner to where the power limiting (form of foldback) takes over at  too low a voltage (in this case it would be say 15A at 4V), otherwise a power bus transient might force the system into a shutdown.

Bob also recommended another way to reduce the charge current, use of the gate dv/dt.  Without going into a long discussion,  this technique can be used where it is desired to uncouple the fault protection timing from the inrush operation/timing.  Generally a "short" fault time is used with a "long" inrush period.  The preak stress is reduced (lower current) at the cost of longer charge.   Keeping in mind that the energy dissipated in the pass MOSFET is equal to the energy storred on the capacitor, the thermal trick is to operate the device at power low enough to (low current = slow charge) allow power to flow into the surrounding heatsinking (assuming the device cannot absorb the energy impulse in one shot - otherwise use the power limit technique).  Some guidance is provided by the MOSFET transient thermal curves. 

If you follow the TPS2490 datasheet, sufficient guidance is provided.  The concept is simple.  If a constant ramp voltage can be applied to the bulk output capacitor (2.2mF), then we know a constant current will flow.  Equation 11 then lets you pick the time required (ex:  dt = 2.2mF x 12V / 5A = 5.28ms) .    Assuming that the MOSFET has high gm, it will operate as a source follower (Vout follows Vgate) if we provide a constant dv/dt voltage to the MOSFET gate.  Equation 12 provides guidance to the total gate capacitance based on the output votlage dv/dt and the gate charge current provided by the TPS2490 (ex: (22uA x (5.28ms/12V)) - 2.5nF = 7.18nF (read on for the Crs used))  .  A little trick we came up with along the way was to come up with an averaged MOSFET capacitance using the Vgs vs Qg plot in most MOSFET datasheets.  The gate charge absorbed as the MOSFET drain falls is represented   by the charge accumulated in the flat part of the curve.  Use this to compute an effective Cgate as C = delta(Qflat)/Vvcc (ex:  (55nC-25nC)/12V = 2.5nF) .  This would replace the Crs term in equation 12.  Tolerances were left to the reader given the short treatment.  So you would probably use a 10 - 15nF cap to ground (with a 1K series resistor) and program a short overload timeout in the <5ms region.

A previous responder seems to have an algebra mistake.