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Original question:

BQ76952: Stacking two ICs

BQ76952: Pin connections in a stacked architecture with HIGH side Mosfets

Ishan Panchal
Intellectual 640 points
Part Number: BQ76952

Hi There,

I went through a previous thread on this link :

After going through this link I am planning to go with the similar architecture for High side mosfets. But I still have some doubts related to certain pin connections listed below :  

  • PDSG pin needs to be connected to FET via a gate driver just as DSG pin ?
  • Where to connect PDSG pin of lower IC ?
  • Where to connect DSG and CHG pin of lower IC ? Do I need to OR these with upper IC pins just as shown in reference design Fig.1 here ?
  • Can I use DDSG and DCHG of upper IC for thermistor interface ?
  • I am planning to use DFETOFF and CFETOFF pins of lower IC with MCU for FET OFF functionality. 

Please let me know..!!!

Thanks..!!!

  • 0
    TI__Guru 54715 points

    Hi Alex,

    • "PDSG pin..." The PDSG pin is intended to drive a high side P-ch FET with a drain current limiting resistor.  Since it is high side it should work fine with a sufficient voltage rating of the P-ch FET.
    • "...PDSG pin of lower IC?" This is left open, the pin is an output.
    • "...DSG and CHG of the lower IC..."  If you are using a external driver like the block diagram in the article, yes leave them open.  If using the internal driver of the top part, also leave the bottom DSG and CHG open.
    • "Can I use DDSG and DCHG of upper IC for thermistor interface ?"  Possibly, but you may want to signal the FET status down, particularly DDSG since the top FET driver can't pull the discharge FET gates below its VSS.
    • "I am planning to use DFETOFF and CFETOFF pins of lower IC with MCU for FET OFF functionality"  Seems like a good plan.
  • 0 in reply to WM5295
    Intellectual 640 points

    Hi WM5295,

    Thanks for the detailed response, I got it..!!!

    Thanks..!!!