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CLKEN not de-asserted down when SYS_CLKREQ on DM3730 is de-asserted

Other Parts Discussed in Thread: TPS65950, DM3730

In order to reduce power consumption when our platform is suspended (RETENTION OFF MODE), we are trying to get the TPS65950 to de-assert CLKEN when the DM3730 goes into an OFF mode.

 

For the record, we are running a rebuild of the TI WinCE 6.0 BSP, version BSP_WINCE_ARM_A8_01_01_00_patch_01_OMAP35XX_AMDM37XX, customized for our specific hardware platform that interconnects the DM3730 and TPS65950 very similarly (but not exactly) as the Minstral 35xx/37xx EVM.

We have setup the TPS registers for CLKEN so that CLKEN does go low in response to SYS_CLKREQ going low, but that doesn’t seem to be happening.

Specifically:

  • CLKEN_DEV_GRP changed to P3 only (write 0x80)
  • LVL_WAKEUP in Px_SW_EVENTS is set to 1. (x=1,2,3; write 0xFF)
  • CLKEN_REMAP changed to 0x00
  • CFG_Px_TRANSITION bit 0 set to allow PWRON key to wakeup the system. (x=1,2,3; write 0xFF)
  • Both DM3730’s SYS_OFF_MODE (connected to nSLEEP1 on TPS) and SYS_CLKREQ (connected to CLKREQ on TPS) are verified to be going low when system suspends.

With those settings, I would expect CLKEN to go low when SYS_CLKREQ goes low, but it does not.

However, if we change CLKEN_DEV_GRP to P1 only (write 0x20), then CLKEN does go low in response to SYS_OFF_MODE going low. However, in this case, the PWRON key can no longer wakeup the system.

What is missing to keep CLKEN on P3, and have it go low in response to SYS_CLKREQ going low?

Alternately, we can move CLKEN to P1 so that it mirrors VDD1 and VDD2 going off, and it goes low in response to SYS_OFF_MODE going low; in this case, why is the power key no longer working, and what does it take for it to still work?

We added some debug to the suspend code to print-out key TPS registers immediately before debug serial goes away when suspending. Here is a dump, with the configuration to leave CLKEN on P3. I can easily add any register if there are additional registers that would be helpful to look at when suspending.

TWL R  [0x4B36] FF  pmm_cfg_p1_transition

TWL R  [0x4B37] FF  pmm_cfg_p2_transition

TWL R  [0x4B38] FF  pmm_cfg_p3_transition

TWL R  [0x4B39] AB  pmm_cfg_p123_transition

TWL R  [0x4B72] 00  pmr_vaux1_dev_grp

TWL R  [0x4B76] 2E  pmr_vaux2_dev_grp

TWL R  [0x4B7A] 2E  pmr_vaux3_dev_grp

TWL R  [0x4B7E] 00  pmr_vaux4_dev_grp

TWL R  [0x4B82] 2E  pmr_vmmc1_dev_grp

TWL R  [0x4B86] 00  pmr_vmmc2_dev_grp

TWL R  [0x4B8A] 2E  pmr_vpll1_dev_grp

TWL R  [0x4B8E] EE  pmr_vpll2_dev_grp

TWL R  [0x4B92] 00  pmr_vsim_dev_grp

TWL R  [0x4B96] 2E  pmr_vdac_dev_grp

TWL R  [0x4B9A] EE  pmr_vintana1_dev_grp

TWL R  [0x4B9E] EE  pmr_vintana2_dev_grp

TWL R  [0x4BA2] EE  pmr_vintdig_dev_grp

TWL R  [0x4BA6] EE  pmr_vio_dev_grp

TWL R  [0x4BB0] 2E  pmr_vdd1_dev_grp

TWL R  [0x4BBE] 2E  pmr_vdd2_dev_grp

TWL R  [0x4BCC] EE  pmr_vusb1v5_dev_grp

TWL R  [0x4BCF] EE  pmr_vusb1v8_dev_grp

TWL R  [0x4BD2] EE  pmr_vusb3v1_dev_grp

TWL R  [0x4BD5] 00  pmr_vusbcp_dev_grp

TWL R  [0x4BDA] EE  pmr_regen_dev_grp

TWL R  [0x4BDD] EE  pmr_nrespwron_dev_grp

TWL R  [0x4BE0] 8E  pmr_clken_dev_grp

TWL R  [0x4BE3] EE  pmr_sysen_dev_grp

TWL R  [0x4BE6] 2E  pmr_hfclkout_dev_grp

TWL R  [0x4BE9] EE  pmr_32kclkout_dev_grp

TWL R  [0x4BEC] EE  pmr_triton_reset_dev_grp

TWL R  [0x4BEF] EE  pmr_mainref_dev_grp

TWL R  [0x4B74] 08  pmr_vaux1_remap

TWL R  [0x4B78] 08  pmr_vaux2_remap

TWL R  [0x4B7C] 08  pmr_vaux3_remap

TWL R  [0x4B80] 08  pmr_vaux4_remap

TWL R  [0x4B84] 08  pmr_vmmc1_remap

TWL R  [0x4B88] 08  pmr_vmmc2_remap

TWL R  [0x4B8C] 08  pmr_vpll1_remap

TWL R  [0x4B90] 08  pmr_vpll2_remap

TWL R  [0x4B94] 08  pmr_vsim_remap

TWL R  [0x4B98] 08  pmr_vdac_remap

TWL R  [0x4B9C] 08  pmr_vintana1_remap

TWL R  [0x4BA0] 08  pmr_vintana2_remap

TWL R  [0x4BA4] EE  pmr_vintdig_remap

TWL R  [0x4BA8] 08  pmr_vio_remap

TWL R  [0x4BB2] 00  pmr_vdd1_remap

TWL R  [0x4BC0] 00  pmr_vdd2_remap

TWL R  [0x4BCE] EE  pmr_vusb1v5_remap

TWL R  [0x4BD1] EE  pmr_vusb1v8_remap

TWL R  [0x4BD4] EE  pmr_vusb3v1_remap

TWL R  [0x4BD7] 00  pmr_vusbcp_remap

TWL R  [0x4BDC] 08  pmr_regen_remap

TWL R  [0x4BDF] 08  pmr_nrespwron_remap

TWL R  [0x4BE2] 00  pmr_clken_remap

TWL R  [0x4BE5] 08  pmr_sysen_remap

TWL R  [0x4BE8] EE  pmr_hfclkout_remap

TWL R  [0x4BEB] 08  pmr_32kclkout_remap

TWL R  [0x4BEE] 08  pmr_triton_reset_remap

TWL R  [0x4BF1] 08  pmr_mainref_remap

TWL R  [0x4B46] 18  pmm_p1_sw_events

TWL R  [0x4B47] 18  pmm_p2_sw_events

TWL R  [0x4B48] 18  pmm_p3_sw_events

TWL R  [0x4B45] 72  pmm_sts_hw_conditions

TWL R  [0x4BE0] 8E  pmr_clken_dev_grp

TWL R  [0x4BE1] 03  pmr_clken_type

TWL R  [0x4BE2] 00  pmr_clken_remap

 

Thanks,

Dave