Hi There,
Looking at the complexity with HIGH side FETs, I have decided to move forward with the LOW side FETs. I have prepared a high level architecture that I would like to send for review in private. But before that, I have certain queries as listed below :
- While using Pre-discharge functionality, Do I need to AND the PDSG pins of both the IC and then drive the FETs ?
- Do you have any suggested circuit for utilizing CFETOFF and DFETOFF pins of both the chips ? I am planning to OR these pins and connect the OR gate output to MCU to detect faults.
- As per reference, DDSG and DCHG pins are used for driving charge and discharge FETs. So, what to do with the DSG and CHG pins of both the chips ?
- As per reference provided by Ti here, Fig.1 shows OR gate for DDSG and DCHG pins but Fig.2 shows AND gates ? As per my understanding the AND gate should be used, please correct if I am wrong.
Thanks..!!!