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BQ76952: Pin connections in a stacked architecture with LOW side Mosfets

Ishan Panchal
Intellectual 640 points
Part Number: BQ76952

Hi There,

Looking at the complexity with HIGH side FETs, I have decided to move forward with the LOW side FETs. I have prepared a high level architecture that I would like to send for review in private. But before that, I have certain queries as listed below :100 

  1. While using Pre-discharge functionality, Do I need to AND the PDSG pins of both the IC and then drive the FETs ?
  2. Do you have any suggested circuit for utilizing CFETOFF and DFETOFF pins of both the chips ? I am planning to OR these pins and connect the OR gate output to MCU to detect faults.
  3. As per reference, DDSG and DCHG pins are used for driving charge and discharge FETs. So, what to do with the DSG and CHG pins of both the chips ?
  4. As per reference provided by Ti here, Fig.1 shows OR gate for DDSG and DCHG pins but Fig.2 shows AND gates ? As per my understanding the AND gate should be used, please correct if I am wrong.

Thanks..!!!

  • 0
    TI__Guru 54715 points

    Hi Alex,

    1. Pre-discharge will be complicated with stacked and low side.  In general pre-discharge should come on any time DSG is about to come on, but DDSG combines both pre-discharge and discharge. So you need logic to keep the main FET off during the PRE- function.  It would be most certain to combine the pre-discharge signals from both parts, but think through the control you want to achieve and test your plans.  TI does not have a reference design example for the circuit.

    2. Consider how you want to control the FETs.  One thought would be to do as you mention with the MCU directly controlling the CFETOFF and DFETOFF signals and combine the DCHG and DDSG signals as shown in the post linked in Q4.  Another would be to have one device's DCHG and DDSG control the other's CFETOFF and DFETOFF through a level shifter.   Since you are looking at low side MOSFETs that signaling would likely flow down, and again you would want to decide where you want to insert the MCU override. A third option would be to have the MCU input to the logic

    3. The DSG and CHG pins are left open on both chips.  They are unused outputs.

    4. Remember that an AND function active high is an OR function active low. You want the FET on only if both devices indicate it is OK, an AND function.  With active high logic an AND gate.  If considering it as a disable, either device should be able to turn off the FET, an OR function.  Use a circuit which combines the signaling you select to the logic control you need.

  • 0 in reply to WM5295
    Intellectual 640 points

    Hi WM,

    Based on your valuable inputs, I am planning to interface the pins as listed below. There are some queries along with the points. Request you to provide your thoughts on same.

    1. PDSG : Considered active low to drive PFET. So OR gate for  combined PDSG pins. Do I need to provide level shifting or isolation for these pins on upper IC while interfacing these pins to MCU via OR gate ?

    2. DDSG and DCHG : Will use reference from fig.2 of stacking reference. And will combine DFETOFF via AND gates and provide it to MCU. Keep the CFETOFF pin NC. Do I need to provide level shifting or isolation for these pins on upper IC while interfacing these pins to MCU ? Will keep CHG and DSG pins NC.

    3. Wake-up (TS2 pin) : Will short these pins of both the IC and connect them to MCU. Do I need to provide level shifting or isolation for these pins on upper IC while interfacing these pins to MCU ?

    Rest of the things seems fine. Request you to accept my connection request so that I can share schematic for review in future.

    Thanks..!!!

  • 0 in reply to Ishan Panchal
    TI__Guru 54715 points

    Hi Alex,

    1. PDSG will drive from high impedance (normally pulled up to the higher of BAT+ or PACK+ through a FET body diode) to V(PDSG_ON), typically 8.4 V below the higher of BAT or LD pin voltage. Yes, you will need to level shift this to the "GND" referenced logic suitable for your MCU or OR gate.

    2. DDSG, DCHG: In Figure 2 of the article https://e2e.ti.com/blogs_/b/powerhouse/posts/how-to-stack-battery-monitors-for-high-cell-count-industrial-applications?keyMatch=STACK%20INDUSTRIAL%20MONITORS there is a level shifter from the top part to the low part and presumable also the MCU reference level. If the MCU provides DFETOFF to the lower part they are at the same reference level and no level shifter is needed.  If the MCU is desired to input to the upper DFETOFF then a level shifter would be needed. 

    3. The TS2 pins will output a 5V pull up when the part is shut down, if connecting to the MCU be sure the MCU input can take the voltage.  More commonly we think this may be controlled by the collector or drain of a signal transistor.  The upper device may be 20 to 60V above the reference of the lower device, so you might use 1 signal transistor and an array of diodes to control both, or use separate transistors to control these again with diodes to avoid pulling the upper TS2 below its VSS, or a level shifter with the pull down transistors at the different reference levels.  Select a circuit that is suitable for your BOM and design.