Part Number: LM5164-Q1
Hi TI,
When LM5164-Q1 is disabled (EN = LOW), the IC shutdown current is a good low 6uA (assume VIN = 48V). However, the pre-IC leakage current can be very high if EN control has been implemented with a pull-up resistor such as on a typical UVLO resistor ladder with open drain midpoint (48V / 100k = 480uA).
In our application, the LM5164-Q1 is the first step on each of multiple ORing power paths so all must turn on discretely before any downstream logic; only then are unused paths are disabled. Because auto-ON is needed, implementing push-pull EN control with a discrete transistor-pair would still require a pull-up resistor to trigger the source transistor in the first place, defeating the point of the original transistor-pair.
A pull-up depletion FET provides the desired normally-ON condition, but we are concerned the negative voltage required for turn-off of each unused power path could greatly worsen the quiescent current consumed by the active power path.
1. What is the highest pull-up resistor value recommended for the EN pin when controlled with an open-drain design?
2. What is the recommended depletion FET design while balancing unused-path leakage-current vs active-path quiescent-current?
3. Is there a different general design altogether that is recommended to minimize total shutdown current while keeping auto-ON and controlled-OFF?
