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PTH08T2xx - Smart Sync control after power on

Alfred Key
Prodigy 200 points

Hello,  I am using the PTH08T2xx series of devices in a Xilinx Virtex6 design and would like to drive the Smart Sync from the FPGA.

To do so the PTH08 must startup in free-run mode (300kHz) and then once the FPGA is loaded it would drive the Smart Sync pin at 240kHz.

Can I use a pull down resistor to GND on the Smart Sync pin and attach it also to the FPGA output?  Then during Boot and Config of the FPGA the Smart Sync pin is held low and after that the 240kHz starts up.  (See sample schematic below).

Also is there any disturbance on the Vout when moving from 300kHz to 240kHz switching?

Thanks, Al...

  • 0
    TI__Mastermind 38230 points

    The PTH08T22X series can  have the sync. signal applied after the output is normalized. The R7 resistor at 33Ω  is to much of a load for any sync. pulses from you r control circuitry.  The minimum high level sync. signal required for good sync. control is between 2.0V and 5.5V. I suggest you increase the resistor to at least 1 kΩ. The reason for  normal grounding of the smart  sync. function is to minimize stray noise from being injected in this pins .

  • 0 in reply to Tom Guerin
    Prodigy 200 points

    Thanks Tom.

    Good catch on the 33ohm resistor.  I will increase it to ~2.2k,  Need to check the drive strength on the FPGA ouput.

    Al...