TPS543B20: Schematic review

Hi Denny,

I have the following suggestions for the provided schematic:

1. I would recommend placing a do not populate capacitor footprint between pins 1 and 2 of the device (this can be loaded with a 100 pF capacitor in the case any filtering is needed of the RSP and RSN connections)

2. I may suggest a 0 ohm resistor placed in series with pin 7 and C101. This resistance may increased to slow down the turn-on time of the high side MOSFET and help reduce SW node ringing if that becomes a concern in the design.

3. For the ground connections, I would recommend having separate nets in the schematic for AGND and PGND with the ground nets connected together using a net-tie or a 0 ohm resistor. In the layout, the ground pours can be connected to a single point (preferably under the thermal pad of the device). AGND should be a "quiet" ground and serve as a reference for sensitive pins of the device such as RT, RAMP, and ILIM. PGND will serve as the "noisy" ground return for the power stage. 

4. VDD may be connected to DC_VIN with a 0 ohm resistor or net-tie. I would then place C10516 as close to pin 26 of the device as possible to provide local bypassing to the input of the controller's power supply. This will help satisfy the TI recommendation for the layout of the TPS543B20 where the trace connecting VDD to PVIN is a separate trace connected to the PVIN plane at a single point. 

The remainder of the schematic looks good to me>

Regards,

Alec Biesterfeld