Hello,
It appears that the SET pin in the logic HIGH state (VIH(set) > 0.75 V) is not modeled. Opening the TPS3702CX33_TRANS.lib file reveals that the SET pin does not have any internal nodes to distinguish between SET HIGH and SET LOW, VIL(set) <0.25 V. To test this in the PSPICE simulation, if a voltage source is placed on the SET pin and stepped between 0V and say 3.3.V, the OV and UV thresholds do not change. That is in conflict with the datasheet.
From what I observe, when SET is grounded (lower tolerance), the UV output follows the data sheet thresholds and the propagation delays nicely. In contrast, if SET is tied to to force VIH(set) > 0.75V, the behavior is the same.
Can you comment on if this is a miss.
Best regards,
Dan
