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LM3495: External Frequency Synchronization

Alexander Osborne
Prodigy 50 points

Part Number: LM3495

I am trying to understand the proper frequency synchronization waveform to apply to the LM3495. The datasheet is ambiguous to me:

  1. On page 3 the absolute maximum rating for the FREQ pin is -0.3V to 6V.
  2. On page 4 the Vsync Hi/Lo threshold is 1.2V/0.3V respectively.
  3. On page 15/16, external clock is to be applied through coupling capacitor Csync (100pF) with the external clock rising above 1.2V and falling below 0.3V.

Here are my specific questions:

  1. Is the Vsync Hi/Lo threshold stated on page 4 the threshold before or after the coupling capacitor Csync?
  2. Is the absolute maximum rating for the FREQ pin on page 3 the rating before or after the coupling capacitor Csync?
  3. What is the DC bias voltage of the FREQ pin?
  4. Is there any restriction on applying a synchronization signal through Csync while the LM3495 is powered off or disabled?
  5. I have a 500kHz square wave switching from 0V to 5V. Is this safe to applying through Csync? Rfrq would be 56kOhm to ground as shown in Figure 33.

Thank you for your guidance,

Alex Osborne

  • 0
    TI__Genius 13451 points

    Hi Alex!

    Our team will reply you soon after weekend.

    Shuai

  • 0
    TI__Expert 5310 points

    Hi Alex,

    To answer your questions:

    1. Is the Vsync Hi/Lo threshold stated on page 4 the threshold before or after the coupling capacitor Csync?
      1. The Vsyncy Hi/Lo thresholds of 1.2V and 0.3V respectively are the logic thresholds after the coupling capacitor (at the pin the of the device).
    2. Is the absolute maximum rating for the FREQ pin on page 3 the rating before or after the coupling capacitor Csync?
      1. The absolute maximum rating of 6V on the FREQ pin is the rating after the coupling capacitor (at the pin of the device).
    3. What is the DC bias voltage of the FREQ pin?
      1. The DC bias of the FREQ pin voltage varies as a function of Rfrq. This will be below the 0.3V threshold in the absence of an external clock. An external clock coupled through a Csync, 100pF capacitor can drive this pin directly and override the DC bias that would otherwise set the switching frequency with an external resistor. 
    4. Is there any restriction on applying a synchronization signal through Csync while the LM3495 is powered off or disabled?
      1. There are not any restrictions in this regard. So long as the voltage of external clock does not exceed any of the pin ratings, this is safe. The device will simply not switch nor regulate when disabled/powered off with an external clock applied.
    5. I have a 500kHz square wave switching from 0V to 5V. Is this safe to applying through Csync? Rfrq would be 56kOhm to ground as shown in Figure 33.
      1. Yes this is safe, the capacitor will couple the square wave external clock to the Freq pin and the amplitudes are within the ratings/logic thresholds of the device.

    Regards,

    Alec Biesterfeld

  • 0 in reply to Alec Biesterfeld
    Prodigy 50 points

    Thank you Alec.

    I suppose my point of confusion is the FREQ pin absolute maximum (minimum) rating of -0.3V.

    If I apply a 5V square wave AC-coupled through Csync, the voltage on the FREQ pin would be whatever its DC bias voltage is (less than 0.3V per your response) plus a +/-2.5V square wave. This would suggest that the voltage at the FREQ pin would exceed its minimum rating?

  • +1 in reply to Alexander Osborne
    TI__Expert 5310 points

    Hi Alex,

    That is a good point regarding the AC coupling of +/-2.5V pk-pk. The voltage specification of -0.3V is typically specified to ensure the ESD diode on the pin is not forward biased without any series resistance (as if one would apply a -0.3V potential without any current limiting directly between the Freq pin and ground). For reference, the ESD diode is a diode with the anode tied to ground and cathode tied to Freq internal to the part designed to protect the device from an ESD (electrostatic discharge) event. I do believe this application should be ok with a 54.9kohm R_FRQ resistance if the pin voltage is pulled below -0.3V and current flows through the diode (the subsequent result will be a clamping in the voltage seen at the Freq pin equal to -1*forward voltage of the ESD diode). This will ensure the pin sees its logic LO threshold, and, assuming a forward voltage of approximately 0.3V, the resulting current through the diode will be on the order of 5.5uA, which I do not anticipate being an issue.

    Regards,

    Alec Biesterfeld