CSD19536KCS: Power Cycle (ΔTj)　and　Heat Cycle (ΔTc)

Hello Sano-san,

Nice to hear from you again. Thanks for clarifying your operating conditions. I can estimate power dissipation from the current waveforms. Are thermal power cycle, ΔTj, and heat cycle, ΔTc, the change in junction temperature and case temperature, respectively? I can estimate ΔTj using the transient thermal impedance curve from Figure 1 on page 4 of the datasheet. However, ΔTc is dependent on the thermal solution (i.e. heatsink, airflow, ambient etc.) for your system.

Referring to the transient thermal impedance curves, for the case of 12sec ON, 5min off, Zθjc = 1 for 4% duty cycle (12s/5min) with a pulse width of 12s.

To estimate the conduction loss in the FET:

P = (Irms x Irms) x Rds_on = (113A/2 x 113A/2) x (2.7mΩ x 1.5), where 1.5 is the normalized on resistance (see Figure 8 on page 5 of the datasheet) assuming Tc = 100°C.

P = 12.9W

To estimate the junction temperature rise:

ΔTj = P x Zθjc x Rθjc = 12.9W x 1 x 0.4°C/W = 5.2°C

This will be the same estimate for 30 minutes or 1 hour on. What I don't know is the thermal time constant of the system so I cannot tell you if the junction temperature will return to the same starting point after 5 minutes off. Let me know if you have any questions or if my assumptions are incorrect.

Best Regards,

John Wallace

TI FET Applications

Hello John-san,

Nice to hear from you and thank you for your comprehensible explain.

I understood the lack of the thermal time constant information. The thermal time constant of our system is 100 sec. 

The things I would like to know is the life time cycle of ΔTj & ΔTc. (I attached the sample of life time cycle graph.)

Could you provide life time cycle of ΔTj & ΔTc in our usage conditions I sent previous question? 

Hi Sano-san,

I have asked our quality reliability engineer to look into this. It is not something that TI typically supplies for our FETs. The curves you have provided appear to be for an IGBT module and we are really not sure how applicable this is to discrete MOSFET devices. The engineer is researching this. I will follow up with you as soon as I have more information.

Best Regards,

John

Hello John-san,

Thank you for your answer and sorry for my late reply.

I understood that the MOSFET heat cycle test was performed after accelerated aging test, and all MOSFET was passed in your test summary.

I agree this demonstrates robustness of the internal solder (die/LF interconnect) and Al wirebond to die.

However , I don't still understand the difference of test method between one chip FET and multi chip power module.

Why does the life cycle test been performed for only multi chip power module?

Why doesn't the life cycle test been performed for one chip MOSFET?

Would you tell me the reason?

Best regards,

Tomomitsu Sano

Sano san,

John is out of the office until Monday, as I have not seen the information provided it is difficult for me to respond. John will answer when he is back in the office.

All I can say is we performed the industry standard MOSFET tests HTRB, HTGB, THB, Autoclave, Intermittent Operating Life (IOL) and Temperature cycle.

Looking at a competitor IGBT module, a qualification report shows themechanical life tests they do  Thermal shock (what we call temp cycle) and Power Cycling (what we call IOL). It appears that IGBT module with multiple die in it does the same mechanical tests that we perform but called a slightly different name.

As I said I do not really know what was sent and John can answer more completely on Monday but I hope this information may help.

Best Regards

Chris

Hello Chris-san,

Thank you for your kindly support. I will wait for John-san's reply!

Best regards,

Tomomitsu Sano