Hello! We are using a TPS2492 based design, and based on the design spreadsheet and physical prototypes, our circuit can use either of two FET part numbers. The PSMN4R8-100BSE or the IPB020N10N5LF. We use two FET's in parallel in this design, and set the power limit to 133W. R4 is 10k, R3 is 80k using the design spreadsheet reference designators.
However, in production testing we see some variation in the measured power limit depending on which FETs are loaded. We'll see between 125W and 137W with the IPB020 FET, but the PSMN4R8-100 will measure lower, 108W to 120W. We figure that our measurement math is not matching up to how the TPS2492 controls the power in the FET. The data sheet makes a quick mention of the power limit in the example, figure 14, where the input current Iin initially climbs to 0.52A and is flat for 5ms or so.
Is the constant power engine design value closest in that initial time after power on? How wide a range will the constant power engine swing to past the designed limit set by the resistor divider?
Thanks!
