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TPS543C20: Output of the regulator ( 0.8V@40A ) is getting dropped to 0.673V when 8A load is applied

Vyshnav vk
Intellectual 440 points
Part Number: TPS543C20
Other Parts Discussed in Thread: TPS546D24A,

Dear TI Team,

1. We are using TPS543C20RVFT IC for the core supply voltage of the main processor in our design. The output is configured to 0.8V 40A.

We started validating the power supply section. The output voltage is stable ( 0.8V ) without any load applied but we see voltage is getting dropped to 0.673V when we apply a 8A load.

Please find the attached schematics section and CRO snapshots of probed voltage in both the cases. 

Kindly go through the issue description and schematics section and provide you feedback on the issue.

2. We are planning to upgrade the design for sourcing 0.8V 80A power by stacking two TPS543C20RVFT regulators for our next revision of board. Please find the stacked regulator design in the second sheet of schematics attached. Kindly review the same and provide your valuable feedback.

Best  Regards,

Vyshnav Krishnan

TI Regulator Output Snapshot.pdfTI Regulator Review.pdf

  • 0
    TI__Expert 5310 points

    Hi Vyshnav,

    I reviewed the provided schematic, and everything for the most part looks good. I would ask if it is possible to provide some follow up details in order to help troubleshoot this issue further.

    1. Is it possible to measure SW when the load is applied (net name = CORE_SNUBBER_M)?

    2. Where is TPH4 located on the layout relative to R130?

    3. If possible, does uninstalling R135 and repeating the test solve the voltage drop issue?

    I suspect the issue is due to instability, measurement location, or current limiting, so those follow up actions would help me better determine the root cause. I entered your design into our excel calculator tool. While the estimated loop bandwidth is high, the design should have sufficient phase/gain margin to ensure stability. A SW node measurement can help confirm this.

    As for feedback on the multi-phase schematic, I would suggest the following:

    1. R1231 may be left DNP. The SYNC pin will set the clock frequency of the secondary device.

    2. I recommend separating the AGND and PGND and tying the nets together at a single point with a net-tie or 0 ohm resistor for layout purposes.

    Regards,

    Alec Biesterfeld

  • 0 in reply to Alec Biesterfeld
    Intellectual 440 points

    Dear Alec,

    Thank you for your quick response and suggestion. 

    1. We will check the suggestions provided by you and debug more on that.

    2. We will update the design as per your input.

    3. We would like to check the loop stability of the stacked configuration. Can we check this using Webench Power Designer Tool.? 

    Best Regards,

    Vyshnav Krishnan

  • 0 in reply to Vyshnav vk
    TI__Expert 5310 points

    Hi Vyshnav,

    In order to evaluate the loop stability, I would recommend Webench and the Excel Calculator tool. I do not believe either of these tools support a stacked configuration. However, if the two phases of the stacked configuration have the same RAMP setting, inductance, and output capacitance, then I would use the single-phase stability analysis as a strong indication of the frequency response/ stability in a stackable configuration.

    The excel calculator may be found here:

    https://www.ti.com/product/TPS543C20#design-tools-simulation

    Regards,

    Alec Biesterfeld

  • 0 in reply to Alec Biesterfeld
    Intellectual 440 points

    Dear Alec,

    OK. We have provided same RAMP settings, inductance and output capacitance for both the regulators. 

    We are able to generate plot ( Gain vs Phase vs Frequency ) using Excel Calculator. Attached the same for your reference. 

    Kindly check it and help us to understand how stable the regulator output is. 

    Best Regards,

    Vyshnav Krishnan

  • 0 in reply to Vyshnav vk
    TI__Expert 5310 points

    Hi Vyshnav,

    The bode plot you shared satisfies the stability requirements TI typically recommends.

    1. The Crossover frequency is ~30kHz, which I anticipate is less than 1/10th of your switching frequency

    2.  The phase margin is approximately 70 degrees. TI recommends greater than 40 degrees, and this is satisfied

    3. The gain margin is in excess of 20dB. TI recommends more than 10 dB

    Regards,

    Alec Biesterfeld

  • 0 in reply to Alec Biesterfeld
    Intellectual 440 points

    Hi Alec,

    Thank you for your feedback. The switching frequency we have configured is 1000KHz ( 1M ). In this case the above values will change or will it remain same.

    Also if we have a pico second transient (up to 100A/120A) can the IC handle it ? Or is there any way to handle this in design.?

    Kindly provide your input.

    Thanks & Regards,

    Vyshnav Krishnan

  • 0 in reply to Vyshnav vk
    TI__Genius 16632 points

    Hi Krishnan,

    Alec will check and reply you soon.

  • 0 in reply to Miranda Gu
    TI__Expert 5310 points

    Hi Vyshnav, 

    I may have answered your question in this thread as well: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1077707/tps543c20-loop-stability-for-certain-loads/3993628#3993628

    Regarding the pico-second transient, I believe the stacked TPS543C20 configuration may handle it, but I do not have a good means of evaluating this on my end. I would recommend a 3/4 phase design using the TPS546D24A to ensure the design can sustain over 100A of current.

    Regards,

    Alec Biesterfeld