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TPS1H000-Q1: Maximum leakage current (+/-) on DELAY and CL pins

Part Number: TPS1H000-Q1

Hi Team,

My customer is performing functional safety analysis for all of the passives on their design and therefore need to understand what the maximum leakage current would be for the DELAY and CL pins on this device. Is this something someone can provide?

Thanks!

Andy

  • Andy,

    Since both the DELAYand CL pins are output pins there are not any leakage spec'ed for them. When operating in latch-off mode, the charging current on the DELAY pin is Idl(chg), however when pulled up or pulled down there are no significant leakage values.

  • Hi Tim,

    Thanks for the quick response! I understand why we don't spec leakage given these are outputs. For some background, my customer follows a different reliability metric than the traditional IEC TR 62380 or Siemens SN29500 that we provide in our safety documentation for FIT rates. They instead follow the FIDES standard, which requires us to determine the power dissipation of each passive component on the design in order to determine the associated FIT rates.

    Given this, I'm trying to understand the power dissipation through the CL resistor & in my instance they are using Auto-Retry mode so am also trying to get an understanding of the power dissipation associated with the pull-up resistor. For this, the pull-up resistance is 10kohm to a 5V supply.

    My assumption is that whatever it is, the current through both of these would be extremely low, likely uA range. Could I make the claim that they would both be < 5uA? Or do we have any characterization data associated with this that I could use as a reference?

    Regards,

    Andy

  • Andy,

    After consulting with the team internally, you can make the assumption that both would be <5uA. We do not specifically have characterization data for these values, however looking over the overall device and discussing internally we can make this statement.