TPS544C25: Power Supply Simulation difference with WEBENCH and PSPICE

Ramakrishna DC

Part Number: TPS544C25

Hi,

We have simulated TPS544C25 in WEBENCH Power Designer with below Specifications:

VinMin = 10.0V
VinMax = 12.5V
Vout = 5.0V
Vout Sch = 5.0V
Iout = 5.19A

With WEBENCH Results, all the parameters looks fine and it meets all our requirements. When the same circuit with same specifications is simulated in PSPICE for TI Tool, it is giving error; Phase margin is not meeting.

With WEBENCH Power designer, the Phase margin shows Phase Marg 47.956 deg. But when we run the same in PSPICE, Phase margin was showing 36 deg.

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/196/TPS544.JPG

1440.5V.pdf

Please Clarify, which simulation we need to consider. Which one is most relabel.

Thanks & Regards,

Ramakrishna D C

Logic Fruit Technologies Pvt. Ltd.

over 3 years ago

0 Miranda Gu over 3 years ago

TI__Genius 16632 points

Hi Ramakrishna,

Our US team will check it and reply you soon.

0 Tomoya Ide over 3 years ago

TI__Genius 11246 points

Hi Ramakrishna,

Let me check with the WEBENCH team and get back to you on this. The WEBENCH should be using the same PSpice average model in the background, so I'm not sure why there is that much difference in the phase margin. For now, please use the PSpice model.

0 Ramakrishna DC over 3 years ago in reply to Tomoya Ide

Prodigy 120 points

Hi Tomoya,

Thank you. we will continue with PSpice simulation.

0 Tomoya Ide over 3 years ago in reply to Ramakrishna DC

TI__Genius 11246 points

Hi Ramakrishna,

To help us debug the issue, would you please share the WEBENCH design URL and PSPICE schematic used for comparison?

0 Praveen Badiger over 3 years ago

TI__Expert 8365 points

Hi Ramakrishna,

We didn't hear back from you.Could you please share the WEBENCH design using the 'Share Design' option and pspcie schematic. This will help us to debug the issue.

Thanks & Regards,

Praveen

0 Peter James Miller over 3 years ago in reply to Ramakrishna DC

TI__Guru 56795 points

Ramakrishna DC

Double check to make sure the external components, including their parasitics such as ESR, ESL, and Capacitor Derating are the same in the WeBench and pSpice simulations. WeBench generally imports these parasitics automatically from it's internal database of components while pSpice simulations often rely on the user to enter these values themselves. Minor differences in parasitic values could shift the poles and zeros of the control loop and thus shift the gain and phase margin.

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TPS544C25: Power Supply Simulation difference with WEBENCH and PSPICE