LM5175: Can LM5175 support pre-bias start up regardless boost, buck and buck-boost mode?

Hi Kazuya-san,

i will try to get the answers to your questions but might need 2-3 days.

Best regards,

 Stefan

Hi Stefan,

Thank you very much for your reply.
I'm looking forward to receiving your answer.

Thank you again and best regards,

Kazuya.

Hi Kazuya-san,

i deleted my previous post as this was within the wrong thread.

For this i still need some more time.

Best regards,

 Stefan

Hi Stefan,

I see. I'm looking forward to receiving your updates.

Thank you very much and best regards,

Kazuya.

Hi Kazuya-san,

Sorry for the delay.  Here are the answers to your questions (in the same order)

A1. Yes it supports output prebias conditions during startup.  Please refer to the datasheet page 18 (here I copy and paste below for your convenience)

A2. Yes VIN pin can be tied to a different voltage rail. It is basically the input for the internal VCC regulator.  VISNS and QH must connect to the actual input power rail. 

A3. Sorry we do not have the data to tell the exact variations of the driver peak current.  However, we usually gives the typical driver peak current in the datasheet.  The actual driver currents are usually seen greater than the typical values in our bench test by driving a pure capacitive load of about 1nF at room temperature. We can assume the driver peak current variation from -20% to +50%.

A4. Sorry, what do you mean by IRHDRV1,2 ? 

Best Regards,

Youhao

Hello Youhao,

Thank you very much for your reply.

And I'm sorry that my No.4 question was wrong.
To be correct, my question is the follow.

Q4. Are there any data of the minimum and maximum value of RHDRV1,2 and RLDRV1,2 of NMOS DRIVERS? 
       Or is there any data of RHDRV1,2 and RLDRV1,2 variation from the typical value? 
       If you have no data, how much variability should we assume?

Could you please give me your reply?

Thank you again and best regards,

Kazuya.

Hi Kazuya-san,

No problem, and I also have typos often:-) 

Sorry we do not have the min and max spec values for the driver internal impedances, but you may be aware that the driver consists of a PFET and an N-FET in totem pole structure.  Hence the RHDRV1,2 and RLDRV1,2 are basically MOSFET channel resistances which would roughly vary from 0.8x at Tj=-40C to 2x at Tj=150C. Also note the following:

• As shown in the datasheet EC-table, RHDRV1,2, and also RLDRV1,2, are greater the driver sourcing the current (i.e. during the ON time of the external MOSFET), and smaller when sinking the current (i.e. in the off state of the external MOSFET)
• RHDRV1,2 and RLDRV1,2 values do not directly determine the driver peak current, because the driver circuit also passes through the linear range of the internal driver MOSFET during the turn-on and turnoff of the external MOSFETs. So the actual peak current is not as simple as VCC / RLDRV1,2 nor (VBOOT - VSW) / RHDRV1,2.   
• For an estimate, we can assume that RHDRV1,2 and RLDRV1,2 may vary up to +/- 20% from the typical value.

Hope these clarify.

Best Regards,

Youhao