TPS6594-Q1: Maximum number of write cycles of internal NVM

Can you elaborate on your use case? Are you trying re-write NVM on the fly and do this multiple times in the field over the lifetime of the device?

-Mike

Hi Mike,

correct, we would like to re-write the NVM each 1-3 days over the whole lifetime to store a 1 bit information for the next power-up.

Cheers, Cornelius

Hello Cornelius,

Writing to NVM would NOT be a good option for this use-case. The process of writing to the NVM requires a couple VCCA power cycles in itself, so I don't think you would achieve the desired result.

I would recommend attaching a coin cell to VBACKUP and using the SCRATCH_PAD registers. There are 4 of them in TPS6594 and their value is only reset when VRTC is disabled. If your system power cycles and VCCA drops below UVLO, the PMIC will switch over to the coin cell and VRTC will be maintained.

we unfortunately do not have the option to implement a coin cell or some comparable alternative (e.g. gold cap,...)

Are the power cycles you are talking about PMIC internal ones, or are outputs affected by writing to the NVM?

Is there a limitation in write cycles?

Cornelius,

At high level the process is

Write to NVM -> power cycle VCCA -> Write to NVM -> power cycle VCCA-> PMIC is ready for use.

Power cycling the NVM will cause the rails to turn off and they may not turn on again until the second power cycle at the end. Therefore, if you are using the processor to do the NVM writes it won't be powered during that second set of writes.

Cornellus,

Mike will be out of office until Wednesday. It appears as though this thread was resolved so if there are other issues to address, feel free to open up a new thread and reference this one if needed. Thank you.

Regards,

Alex