Hello,
We have a pull up to 5V with a 10k resistors on the PG pin. The pin drives an input to a logical nor gate, and the input capacitance of this component is 10 pF. According to the data sheet, there is a "deglitch" time of the PG pin of 25 us.
What is the minimum low time of the PG pin? When the output voltage is out of range or when the EN pin is below a threshold (~2V), the PG is pulled low. This "dip" in the PG affects the "downstream" electronics of our design. A very short "dip" in the PG could cause problems, whereas a longer "dip" would not
.
Thank you for any answers!
