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TPS650864: THOT and TCRIT asserted at same temperature and causing momentary shutdown of rails

Part Number: TPS650864

Hi E2Experts,

I have multiple boards designed with TPS6508640 powering a Xilinx ZU3 and ZU2 MPSoC and am seeing some unexpected behavior consistent with all of them related to operating temperature of the TPS6508640.

What we are seeing:

The datasheet specifies the PMIC will enter emergency shutdown (section 8.10.7 in SWCS138D) when TCRIT is reached, and that temp is in the DS as min 130C.  No mention of THOT is made in this section.  Behavior of the TPS6508640 when reaching THOT is not described in the DS but can be inferred from the lack of info that no rail sequencing is expected at this threshold.

Yet we are seeing TCRIT being improperly asserted in the register 0xB4 at a case temp of ~110C.  From the Psi-JT parameter and our total dissipation on the entire board being <6W, Tj is expected to be ~112C, far below the TCRIT value. 

The erroneous assertion of TCRIT correlates to the momentary shutdown of our power rails that are immediately resequenced because our ENABLE PIN (CTL3) is tied to a power good indication from a supervisor looking at the TPS6508640's input voltage.

When we exceed a case temp of 130C, no flags change in the registers as TCRIT was already asserted at the THOT threshold, then we see the expected and described emergency shutdown where rails drop discharge and remain discharged until the case cools to ~TCRIT-TCRIT_HYS. 

So can you please help explain why the TPS6508640 momentarily brings the rails down when passing the THOT threshold.  Where in the DS it describes this behavior?  Where we can find a description of the thermal monitoring block as shown in the PMIC Functional Block Diagram.  And is there something that can be done to bypass this behavior?

Best Regards,

Rob Rodrigues

  • Hello Robert,

    We have assigned this thread to the appropriate engineer and she should be able to get back to you by Friday. Thank you.

    Regards,

    Alex

  • Hi Robert,

    Thanks for your patience!  As you know, this thermal issue is being discussed by email as well. We will take some measurement in the lab using the EVM and should be able to provide an update by next Wednesday. I also wanted to make sure my feedback and questions on the schematic was received on your end. Please find the notes below.  

    • Why are you using 6.8uH inductor on Buck3 and 2.2uH on Buck5? As noted in the datasheet, the three Buck converters (Buck3/4/5) are optimized for either a 0.47uH or 1uH. Other values could be used but they have to be carefully selected following equations 5/6 in the datasheet and using the data on the switching frequency plot. Could you provide more details on how those inductors were selected? 
    • If TPS6508640 (this variant specifically) is used, then Buck4 must have its external components. This rail is part of the power-up sequence and it’s corresponding internal PGOOD signal is needed to properly enable the next rail which is Buck3. Forcing a voltage on the FB pin could be a work around to bypass the internal power good a prevent a shutdown but we prefer our customers to use TPS65086100 (user programmable version) when custom OTP settings are needed.  
    • One of the GPIOs (GPO4) is missing its pull-up resistor.
    • Could you complete the layout checklist and send it back to us? Here is the link: TPS65086x Schematic and Layout Checklist (Rev. A). If you could also share the portion of the layout that includes the PMIC and its external components that would be very helpful. This can be shared by private E2E message. 
    • Were the equations in the datasheet (section “9.2.2.1 Controller Design Procedure”) used to calculate the inductor and capacitor values of the buck controllers (Buck 1/2/6)? What is the max load current expected on each of the buck controllers?

    Thanks,

    Brenda