Dear expert,
For below description from technical reference manual:
"The I2C clock stretches may occur after start bits, the ACK/NACK bit, and first data bit transmit on a host read cycle."
All I2C clock stretches only happen on read cycle? Or only first data bit transmit on a host read cycle?
The I2C clock stretches may occur after start bits. Then it can happen between any bits?
The I2C clock stretches may occur after the ACK/NACK bit? ACK mean the transmission already success why clock stretch is still needed?
Customer BQ27Z561-R1 meet I2C hangup issue randomly with Qualcomm processor.
As below capture, (Blue is SCL, purple is SDA), you can see after ACK, SCL keeps low for around 300ms (You can refer to upper zoom out picture) and then goes to high. And SDA is high after ACK and become low after around 100ms. Then the I2C bus hang up(no any signal change). (Only 561 is at this I2C bus)
Need you help to answer my above questions and give me more hint if you have.
great thanks
