TPS3828-33 Remaining Continuously in Reset (Reset# Does not go High)

Sharwari Kulkarni

Intellectual 490 points

Other Parts Discussed in Thread: TPS3828, TPS3823

Hello,

I am using TPS3828-33 for generating the reset for an FPGA.

The following are ths status of the pins of the TPS3828-33

1. RESET# (Output, no pull up, goes to FPGA)

2. GND (Connected to GND).

3. MR# (Input, connected to a switch with a pull up).

4. WDI (NC, left unconnected).

5. VDD = 3.3V

The output RESET# is remaining low always and never becomes high. What could be the reason for this? Does leaving the WDI input open disable the watchdog ?

Can anyone help me out?

Regards,

Sharwari

over 14 years ago

0 Chris Glaser over 14 years ago

TI__Guru**** 150900 points

Yes, the TPS3828 has an open drain reset output. This requires a pull-up resistor to go high. This is noted on page 1 of the datasheet.

Yes, WDI may be left floating to disable it. This is noted on page 2 of the datasheet.

I recommend replacing the TPS3828 with the TPS3823 which has a push pull, active low output or adding a pull-up resistor on /RESET to your current circuit.

0 Sharwari Kulkarni over 14 years ago in reply to Chris Glaser

Intellectual 490 points

Hello,

I added a pull up resistor for RESET# output and now the reset scheme is working when I disconnect the WDI input.

However now when I connect the WDI input giving a 2MHz 3V3 signal from the FPGA to the WDI input, the TPS3828-33 is remaining in continuous reset.

What could be the reason for This?

Sharwari

0 Chris Glaser over 14 years ago in reply to Sharwari Kulkarni

TI__Guru**** 150900 points

Is the WDI active before the SVS leaves RESET? If so, then you need the circuit in figure 1, page 2 of the datasheet.

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TPS3828-33 Remaining Continuously in Reset (Reset# Does not go High)