Hello,
I am using TPS3828-33 for generating the reset for an FPGA.
The following are ths status of the pins of the TPS3828-33
1. RESET# (Output, no pull up, goes to FPGA)
2. GND (Connected to GND).
3. MR# (Input, connected to a switch with a pull up).
4. WDI (NC, left unconnected).
5. VDD = 3.3V
The output RESET# is remaining low always and never becomes high. What could be the reason for this? Does leaving the WDI input open disable the watchdog ?
Can anyone help me out?
Regards,
Sharwari