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Original question:

TPS650864: BUCK controller output dips during startup

TPS650864: Power Down Sequence

Teik Hooi Teoh
Intellectual 655 points
Part Number: TPS650864

Hi,

For my power down sequence of TPS65086401 (as the PMIC for XIlinx Zynq US+ MPSoC), we observed the below:

  • CTL1 starts to power down later than the other outputs
  • Some abnormal steps in GPO1 / CTL6 , GPO3 / CTL4 and GPO2

 The reference power down sequence seems to be should be like this:

Is the power down sequence acceptable? What can be possible causes.?

  • 0
    Intellectual 655 points

    P06_pwrdwn.zip

    sorry...forgot to attach the power down sequence waveforms.

  • 0 in reply to Teik Hooi Teoh
    TI__Mastermind 22156 points

    Hi Teik,

    It seems like the PMIC is executing an emergency shutdown. The main supplies VSYS, V5ANA, PVINx which comes from external regulators are shutting down before the CTLx pins go low.

    If the external supplies are removed from the PMIC, then the PMIC will not have power to execute a sequenced power down.   

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Intellectual 655 points

    Hi Brenda,

    I am just thinking, would not that be the normal case where the external sources (e.g DC input from AC adapter to the system) drop to low before the PMIC can detect to shut down?

    Btw, how would the PMIC detect power off in this case?

    As I have shared in another related forum thread, my CTL2 is pull-up to LDO3P3.

    Probably this should be the main reason that holds back the CTL1. 

    But does it affect other CTLx pins as well?

    In the case of this emergency shutdown, would it cause any latched up or damage to the PMIC?

    Thank you

  • 0 in reply to Teik Hooi Teoh
    TI__Mastermind 22156 points

    Hi Teik,

    A power down sequence and an emergency shutdown are executed under different conditions. The power down sequence, just like the power-up, can be controlled with the CTLx pins, the power good of a previous rail and delays. This can be done while the external supplies VSYS, V5ANA and PVINx are connected. On the other hand, the Emergency Shutdown will be executed when VSYS crosses below the UVLO threshold. Other conditions that will cause an emergency shutdown are described in the image below (from datasheet). The reason why you are seeing some of the CTLx pins going low after the rails are shutdown is because there are two VSYS UVLO thresholds; one is called  VSYS_UVLO_5V and the other VSYS_UVLO_3V. 

    • UVLO Thresholds

    • EMERGENCY SHUTDOWN

    • POWER DOWN SEQUENCE CONTROL

    Thanks,

    Brenda