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UCC28070: About Current Synthesizer

Kaji@PAN
Mastermind 7805 points
Part Number: UCC28070

Hello,

I'm using UCC28070 to create a bridgeless circuit.
In addition, current detection consists of low resistance + OPAMP.
I asked about this earlier in the thread below.

This time I would like to ask you a question about the Current Synthesizer.
The OPAMP gain of the current detection circuit was increased for the purpose of improving the PFC operation near the AC zero cross.
Then, when the AC input was reduced under the rated load condition, the PFC output voltage dropped. It drops to 280V from the set value of 390V.
Switching continues, but the voltage remains low.
The cause was that the OPAMP gain for current detection was increased, but the RSYN resistance was not optimized.
It was improved by changing RSYN, but the reason for the improvement is unknown.

(Question 1)
What is the reason for improvement by changing RSYN?
(Question 2)
The PKLMT setting is about 3V, but the input voltage to CAx(OPAMP output) is set to about 1.5V.
Is this setting okay?
(Question 3)
Is it possible to monitor the down-slope of the Current Synthesizer?
Can you monitor with a pin somewhere on the device?

Best regards,

e2e.ti.com/.../ucc28070-bridgeless-circuit-using-resistor-opamp-instead-of-current-transformer-for-detection

  • 0
    TI__Genius 11350 points

    Hello Kaji,

    Sorry for the delay. I will respond to your questions tomorrow.

    Ray

  • +1
    TI__Genius 11350 points

    Hi Kaji,

    1. The synthesized downslope is determined by the current developed in Rsyn. Since you increased the amplitude of the signal into CA, you increased the amplitude of the current upslope. However, by failing to reduce Rsyn to compensate, the downslope won't get as low as the starting level of the next current upslope. This results in a deformed waveshape which shows a higher average current than actually exists. The CAs will thus lower the duty cycle to make the average synth waveform follow the Vimo reference. Vvao will increase to a higher level to keep the output in regulation.  However, as the line voltage decreases, VINAC and therefore Iimo decrease and Vvao need to increase to restore Iimo. The average synthesized current is still overstated, so the CAs reduce the duty cycle further until eventually, Vvao reaches the 5V clamp. From here, Iimo will increase if VINAC crosses a Kff threshold. Eventually however, the Kff reaches it's lower end and Iimo can only decrease as the line voltage continues to decrease (resulting in higher input current), reducing the power limit and causing the output to drop.

    2. If highest CSx signal is 1.5V under normal maximum circumstances, a 3V limit would allow 2X the peak inductor current.
    This could happen during a line transient event with a step-increase in input voltage, however, it is recommended to set PKLMT to 110%~120% of the normal max CSx signal (1.5V in this case, so PKLMT = 1.65~1.80V).

    3. There is no way to monitor the downslope of the current synthesizer.

    I hope this helped.

    Regards,

    Ray