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Original question:

BQ25790EVM: Typo in guide, error in GUI Composer, or otherwise failing to write Charge Voltage Limit in GUI Composer

BQ25790EVM: Charge Mode Verification Issues

Christopher Buckley
Intellectual 330 points
Part Number: BQ25790EVM

Following along with the User Guide I have made my way to Section 2.4.3.3 and note that I am not measuring " IBAT_SENSE (voltage across 0.01 ohm resistor between TP17 and TP18) = 240 mA ±60 mA"

Furthermore it looks like I'm seeing flickering faults on VBAT_OVP_STATUS and VSYS_OVP_STATUS. From playing around with the order of operations, it seems I need to have my battery simulator enabled prior to turning on PS #1, else I enter this fault state. The guide, in Section 2.4.3.1 simply says they both should be on from Section 2.4.1, which says to turn them both on in 2.4.4 but in no particular order.

The guide Section 2.4.3.2 states that I should have both PS #1 and Load # 1 ON, then reinstall the J19 jumper (Section 2.4.3.2) to enable charge. This order of operations causes the faults mentioned above.

What seems to work is to have only Load # 1 ON (a battery simulator) with jumper J19 installed, then turning on PS #1. Any other order seems to result in some faults and no charge occurring.

Any hints as to why this is the case?

  • 0
    TI__Guru**** 153936 points

    Hi Christopher, 

    Please see the FAQ at 

    https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1023437/faq-bq25792-why-does-the-sys-output-of-the-evaluation-module-evm-collapse-when-no-battery-or-battery-simulator-is-attached-to-the-bat-pins

    In short, the EVM simulates a thermistor always being present. So when there is no battery or simulator at BAT, the BAT pin overshoots causing OVP.  In most real systems, when the battery and thermistor are removed, charge is automatically disabled due to TS fault.

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Intellectual 330 points

    Thanks Jeff.

    As per the FAQ, " To prevent the SYS voltage from collapsing when the battery is removed or is not present, remove its thermistor earlier or at the same time as battery removal or disable the simulated thermistor on the EVM using the headers and shunts. " how exactly would I disable the simulated thermistor on the EVM? From the schematic it looks like the TS pin is hard wired through R26 to GND with other shunts controlling various temp simulations. Do I disconnect JP14 to remove REGN? The pin description in the guide says, "This must remain connected" so I'm a bit hesitant to just try.

    Also apart from how to avoid this, how would one recover from this state via the host? Are there ways to get out of this state via some registers? I guess if I am in this state and the battery simulator is definitely not in an OV level, why would the BAT pin remain in OVP? I'm not seeing anything in the datasheet that clearly describes how to escape or reset these fault states. The only thing related to V_BAT_OVP I see is in the Electrical Characteristics where it states



    So assuming I am in the 1s default config via the PROG pin, you're saying V_BAT went above 4.2 * 1.04 = 4.368V when the battery simulator was disconnected, but after I reconnect, I'm at 4.05V. Shouldn't this register as VBAT "falling, as percentage of VREG" below 102% of VREG?

    Is there no way to recognize I'm no longer in a faulty state without power cycling PS #1?

    Best regards,
    Christopher

  • 0 in reply to Christopher Buckley
    TI__Guru**** 153936 points

    Hi Christopher,

     This IC was designed assuming that the thermistor will be removed when the battery is removed.  To simulate a real battery and its thermistor being removed, you would remove JP18 which connects the 10kohm resistor that is simulating a thermistor before the simulated battery is removed.  Or you can disable charge by removing JP17 or the CE register bit.  If charge is disabled via TS fault or CE bit or pin, OVP does not occur. 

    Regards,

    Jeff