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TPS51124: Understanding dead times

Oliver Filsch
Intellectual 440 points
Part Number: TPS51124


Hello,

we have to change the top FET in an existing design with TPS51124.

When examining the switching using the given min. dead times in the datasheet (10ns / 30ns), a shoot-through could appear with the new top FET when the bottom FET turns on, because the top FET's turn-off time is too large.

To my question: the datasheet gives information of dead times, min./typ./max. values. Are these fixed values?

In other words, are fixed dead times implemented in the device, or is there an adaptive / cross-coupled technique used to prevent shoot-through so there will be no problem using the new FET?

Thanks in advance,

Oliver

  • 0
    TI__Guru 56985 points

    Oliver,

    Yes, the TPS51124 implements adaptive gate drive dead-time control.  This is shown in the datasheet on the functional block diagram (Section 7.2)

    On the high-side turn-off to low-side turn-on transition, the high-side gate drive circuit monitors the LL to HDRV voltage and inhibits the turn-on of the LDRV pull-up, until the HDRV to LL voltage drops below 1V.  Once the high-side gate drive voltage (HDRV - LL) is detected below 1V, the comparator output must level shift to the low-side FET.

    In order to maximize the effectiveness of this dead-time control, it is important to minimize external series resistance on the HDRV and LDRV gate drives signals.  These resistances allow the HDRV sensed voltage to fall faster than the  actual MOSFET gate voltage.

    It is, however, unusual that you are seeing a potential dead-time control violation on the HDRV falling to LDRV rising, where typically the low-side FETs turns on slower than the high-side FET turns off, but the Adaptive Dead-time Control circuit ensures part of the high-side FET turn-off time occurs before the low-side FET can start to turn-on.

  • 0 in reply to Peter James Miller
    Intellectual 440 points

    Dear Peter James,

    thanks a lot for the explanation of the dead-time control function!

    One thing still is not entirely clear to me yet. In the datasheet:

    - dead time DRVHx-low (DRVHx = 1 V) to DRVLx-on = 20ns (typ.)

    - dead time DRVLx-low (DRVLx = 1 V) to DRVHx-on = 40ns (typ.)

    The first one is the high-side turn-off to low-side turn-on transition, right? Here, this dead time is smaller than the second dead time (low-side turn-off to high-side turn-on), whereas the first one should be larger than the second one as you mentioned. Or is the text in the datasheet to be understood in another way?

  • 0 in reply to Oliver Filsch
    TI__Genius 16632 points

    Hi Oliver,

    Peter will check your questions next Monday. Tomorrow is public holiday. Appreciate your understanding.

  • 0 in reply to Oliver Filsch
    TI__Guru 56985 points

    Oliver,

    No, you are correct.  I had them mixed up.  My apologies for that.  I will correct the text above.

    Both drivers suffer from the level shifter delays, however the LDRV falling to HDRV rising delay is longer.  That was my error in reading the two values.

  • 0 in reply to Peter James Miller
    Intellectual 440 points

    Dear Peter James,

    thanks for clarification!