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BQ40Z80: Kindly review the scheme

saneesh P S
Prodigy 60 points
Part Number: BQ40Z80

Hi Ti Team,

I have shared the snapshot of the schematics for Review. BQ40Z80 is employed for Li ion  Battery pack . Battery pack Consists of 3S combinations of 3.6V Li ion cells. Maximum Continues Discharge Current is 30A and Maximum Charging Current is 2C(1C = 2.5Ah). External Cell Balancing Circuit added for Fast Cell Balancing. Kindly review the scheme

  • 0
    TI__Guru** 105760 points

    Hello Saneesh,

    I have a few comments:

    • You can reduce the gate to source resistance on the CHG FET to zero if you would like. For DSG, going below 2k Ohm will cause issues with support of reverse charger survival.  If you don’t need reverse charger support, then the DSG FET resistance can drop to zero as well.
    • I think your cell connection points are not connected properly, the VC1 should be top of cell one, not tied to ground which it appears from the schematic. Also I would recommend taking a look at some other threads for cell balancing, it is recommended to use a P_FET for the first cells external balancing: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/342036/bq40z50-external-cell-balancing
    • I can't see all the cross page reference nodes so I cannot verify them. Also it looks like some of the node naming for the top of stack is inconsistent, BAT+ should basically be VC3 (top of stack for the configuration you're using)
    • I would recommend increasing the PBI capacitance if you reduce the series gate resistance from DSG and CHG pins, over 5uF should be sufficient if your FET gate capacitance is not too high.

    I would recommend comparing your schematic with the EVM schematic while designing the schematic, this should help you catch most of the small issues.

    Sincerely,

    Wyatt Keller

  • 0 in reply to Wyatt Keller
    Prodigy 60 points

    Hi,

    Thanks for the immediate response. Response Against your Queries added below

    1. You can reduce the gate to source resistance on the CHG FET to zero if you would like. For DSG, going below 2k Ohm will cause issues with support of reverse charger survival.  If you don’t need reverse charger support, then the DSG FET resistance can drop to zero as well. Response:  Do you mean Gate Resistance or Gate to source Pull down resistance here?
    2. I think your cell connection points are not connected properly, the VC1 should be top of cell one, not tied to ground which it appears from the schematic. Also I would recommend taking a look at some other threads for cell balancing, it is recommended to use a P_FET for the first cells external balancing: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/342036/bq40z50-external-cell-balancing . Response: Understood
    3. I can't see all the cross page reference nodes so I cannot verify them. Also it looks like some of the node naming for the top of stack is inconsistent, BAT+ should basically be VC3 (top of stack for the configuration you're using). Response: Understood. 
    4. I would recommend increasing the PBI capacitance if you reduce the series gate resistance from DSG and CHG pins, over 5uF should be sufficient if your FET gate capacitance is not too high. Response: What is mean by PBI Capacitance? 

    Best regards

    Saneesh

  • 0 in reply to saneesh P S
    TI__Guru** 105760 points

    Hello Saneesh,

    1:

    Sorry I was referring to the gate to source resistance, but I also wanted to point out having 0Ohms going from the CHG/DSG pin of the gauge to the gates of the FETs - this may need a higher capacitance on the PBI pin. Right now you have a 2.2uF capacitor on the PBI pin which is the "power buck up" and it is used by the charge pumps to pull charge quickly.

    Sincerely,

    Wyatt Keller