Hello,
May I ask some questions on TPS546D24's VDD5 operation?
(1) My customer is considering to utilize the internal VDD5 output to the external circuits - FET gate pull-up voltage. Even though the datasheet mentions not recommended, I think customer can use it because FET gate pull-up would not consume much of current. Pull-up resistor would be 100k, thereby ~50uA (=5V/100k). Please advise if you have concern here.

(2) Is VDD5 always-on regardless of EN/UVLO pin level, once AVIN reaches its VULO level?
(3) It's little confusing with UVLO. AVIN has UVLO of 2.5V, then the internal 5V regulator will start to turn on once AVIN > 2.5V. But VDD5 outputs 4.7V with 130mV dropout. How AVIN 2.5V can turn on the internal 5V regulator?
(Customer ties PVIN and AVIN together to 12V.)

(4) When it comes to UVLO level and VDD5 operation, TPS546D24 and TPS546C24A would show the same operation. Could you confirm?
Thank you.