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TPS650864: startup time of LDOA1/2/3 vs LDOAx and minimum startup time

Kai Nomiyama
Expert 5605 points
Part Number: TPS650864

Hi Team,

I have three questions about TPS6508641 so could you support?

device: TPS6508641

#1: LDOAx
What is the difference between 7.9 electrical characteristics: LDOA1/2/3 tstartup ~500us_max vs 7.15 Switching Characteristics
LDOAx tstartup 180us_typ?


#2: minimum start-up time
What is the minimum tpg(total turnon time) of BUCK CONTROLLERS, BUCK CONVERTERS, LDOAx, SWA1 and SWB1_2?
MPSoC requires 0.2ms_minimum ramp time from GND to 95% of Vcc_xxx.


#3: LDOAx minimum start-up time with 2.2, 4.6 or 10uF output capacitor
LDOAx startup time is "Measured from EN = H to reach 95% of final value".
this means LDOAx start-up time should be controled internally inspite of output voltage.
Even if we change output capacitor from 4.7uF to 2.2 or 10uF, we can apply the same LDOAx start-up time of #2 answer of LDOAx minimum startup time?

Regards,
Kai

  • 0
    TI__Mastermind 22275 points

    Hi Kai,

    1) The t_startup found in 7.9 shows the max startup time for LDOAx (500us). The max time is not related to a specific voltage output setting. The t_startup from 7.15 shows the typical startup time for LDOAx (180us). This typical value was measured specifically at Vout = 1.2V

    2) BUCKS 1-6 have a minimum soft-start time of 200us before slewing up to their set voltage output values at the rates shown in Section 7.7 and 7.9 (See SR(Vout) parameter). The LDOs and Load Switches do not have documented minimum startup times. If you designing for the Zynq Ultrascale+ MPSoC, then the PMIC options shown in the application note linked below will be specifically designed to work with the system without timing issues.

    Using TPS65086x PMIC to Power Xilinx Zynq UltraScale+ MPSoCs

    Usually the main concern is sequence timing on power up and slew rate of the regulators. Following the recommended component selections should prevent sharp spikes in regulator startup waveforms.

    3) The LDOAx startup time is measured with output voltage at 1.2V and a 4.7uF capacitor specification. Changing these component and output values can alter the the startup time from the recorded typical value and will also influence the minimum possible startup time. There is no hard set minimum start up time but the signal can be influenced by external component choices. More capacitance can be used to slow down the startup times.

    The same is true for the Load Switches, which were tested with a 0.1uF capacitor at two different input voltages (VIN = 3.3V and VIN = 1.8V). Start up times of SWA1 and SWB1_2 for VIN = 1.8V are ~ 200us to 300us faster than at VIN = 3.3V.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Expert 5605 points

    Hi James,

    Let me double check #3?

    My understanding for soft start is tss follows Css ramp.
    Internal current source charges Css and Vout follows Css ramp.
    Internal current source and Css are fixed value so soft start time should NOT have correlation with Cout and Vout.

    However, you said "More capacitance can be used to slow down the startup times.".

    Does it mean TPS650864 controls soft start time by constant current control during startup?
    If soft start is constant current control, your comment makes sense.

    Regards,
    Kai

  • 0 in reply to Kai Nomiyama
    TI__Mastermind 22275 points

    Hi Kai,

    Changing the components from what was used in the datasheet, such as adding external capacitance or increasing the Vout value will change the start-up time of the LDOs. Soft start is not referenced for the LDOs in the datasheet, but even so, the LDO start-up time can still be increased with more capacitance at the output or with a higher output target.

    Overall, there should not be an issue with start-up times for this device in relation to the Xilinx devices since Xilinx has approved our solution on their power partners page.

    Regards,

    James