Hi team,
I would like to confirm the WDI timing requirement after the Watchdog reset.
When WDI violation occur and WDO goes LOW, then after trst, WDO goes High again. Does the watchdog timing initialized at this WDO LOW to High timing?
Or watchdog logic continues during WDO is LOW, then the watchdog timing is only determined by the WDI falling edge?
I plan to use WDO signal to reset the MCU. So I would like to know the first WDI pulse requirement after WDO rising edge is t <twdu(min) or twdl(max) <t<twdu(max).
Regards,
