UCC5870-Q1: SPI TX CRC check

Hi Tobias,

We currently do not have an example code for the CRC usage. Let me review your implementation and I can provide an update next week.

Best regards,

Andy Robles

Hello Andy.
Do you have a CRC using example for me?
At the moment I don't use the CRC function.
Thanks Tobias

Hello Tobias,

Thank you for your response!  Andy is out at the moment, but should get back to you by the end of the week.

-Aaron

Hi Tobias,

Thank you for your patience.

Tobias Haerter said:

1. I could no read the TX CRC data from the CRCDATA register. The values change every time. What is wrong at my implementation.
I write to the TX CRC register and then read it, but the read value change every time.

When you write to the CRC_TX bits in the CRCDATA register the gate driver will do a comparison between the stored CRC_TX data and the value you wrote to this register. After the comparison the gate driver will reset the CRC_TX data bits to its default value 0xFF.

• Just to clarify, every time you write to the CRC_TX data bits, which resets the CRC_TX bits to the default values 0xFF, you then send a read command to read this register and you get a different value every time? (i.e. Only write and read commands are sent to the CRCDATA register, no other commands are sent)

Tobias Haerter said:

but if I write a wrong CRC value to CRCDATA I don't get the fault status

I see in your example you sent the wrong CRC data to trigger the fault (Calculation should be 0x30 like the datasheet example, but you sent 0x00).

• Could you confirm when you say you did not get a fault status you mean you read the STATUS2 register bit 9(SPI_FAULT) and did not see a fault (bit 9 = 0x1; fault)?

Tobias Haerter said:

3. If I write to SPITEST I don't get the fault status.

• This is unusual. Writing a non-zero value to this register should trigger a STATUS2 register bit 4(CFG_CRC_PRI_FAULT).
  
  • Could you confirm weather you see any faults in any STATUSx register trigger when you write to this register?

Best regards,

Andy Robles

Hello

I think I have some basic understanding problems.
Ho do I get a SPI fault:
With the code:

    // reset CRC
    ctrl1.all = 0;
    ctrl1.bit.CLR_SPI_CRC = 1;
    ucc5870_write_register( select, OFFSET_CONTROL1, ctrl1.all );
    // test SPI CRC fault
    ucc5870_write_register( select, OFFSET_SPITEST, 0x1818 );
    ucc5870_read(select, OFFSET_STATUS2, &read);

I read always 0x4004 at status 2 register.

Thanks for your help.

Sorry I have done a mistake pressed the "resolved" button

Hello.
Yes the CRC_DIS bit is 0.

    // enable CRC check
    cfg8 = ext_df_default_config.CFG8;
    cfg8.bit.CRC_DIS = 0;
    ucc5870_write_register( select, OFFSET_CFG8, cfg8.all );
    ucc5870_read(select, OFFSET_CFG8, &read);
    // => read = 0x0028
    // reset CRC
    ctrl1.all = 0;
    ctrl1.bit.CLR_SPI_CRC = 1;
    ucc5870_write_register( select, OFFSET_CONTROL1, ctrl1.all );
    // test SPI CRC fault
    ucc5870_write_register( select, OFFSET_SPITEST, 0x1818 );
    ucc5870_read(select, OFFSET_STATUS2, &read);
    // => read = 0x4000 

Are there any other setting missing?

Thanks for your help.
Tobias

Hi Tobias,

Thanks for the information!  Andy will get back to you soon!

Thanks,

Aaron

Hi Tobias,

Besides the writing a 0 in CFG8 register bit6(CRC_DIS) to enable configuration CRC there is no other setting needed to trigger the SPI_FAULT besides being in the active state.

• In your example code I see you wrote to config register then wrote to SPITEST register without going into the active mode. Can you add the step to go into the active state before writing to the SPITEST register?

Best regards,

Andy Robles

Hello.
I have add a function to enable the UCC5870.
I have add a check of the state to my example and I think the UCC5870 is active.

// set active
ucc5870_enable(select);
// read status
read = 0;
ucc5870_read(select, OFFSET_STATUS1, &read);
// => read = 0x00C0 => active mode ???

// enable CRC check
cfg8 = ext_df_default_config.CFG8;
cfg8.bit.CRC_DIS = 0;
ucc5870_write_register( select, OFFSET_CFG8, cfg8.all );
read = 0;
ucc5870_read(select, OFFSET_CFG8, &read);
// => read = 0x0030

// reset CRC
ctrl1.all = 0;
ctrl1.bit.CLR_SPI_CRC = 1;
ucc5870_write_register( select, OFFSET_CONTROL1, ctrl1.all );
// test SPI CRC fault
ucc5870_write_register( select, OFFSET_SPITEST, 0x1818 );
read = 0;
ucc5870_read(select, OFFSET_STATUS2, &read);
// => read = 0x4004

Hi Tobias, 

Thank you for your question. Our office is closed today for a US holiday. Our colleague will get back to you by tomorrow.

Best regards,

Leslie

Hello
Sorry, I have found a bug in my function ucc5870_write_register so that all write to Control registers are failed.
Now the example with the SPITEST work in active mode but not in Configuration 2 mode. But I Think it should also work at  Configuration 2 Mode?

Hi Tobias,

This fault only works in active mode. This is due to the register being protected by the configuration CRC feature (described in section 7.3.5.16). When the gate driver goes into active mode the gate driver runs CRC calculations using the data in the registers protected by this feature which includes the SPITEST register. The gate driver then stores this value and uses it as the baseline. The gate driver then performs periodic calculations on the protected registers and compares the new calculated value with the baseline value that was calculated when the driver first transitioned to the active mode. If the values don't match then the STATUS2 register bit 4(CFG_CRC_PRI_FAULT).

Writing to the SPITEST in the active will change the CRC calculation which will create a mismatch that then trigger the STATUS2 register bit 4(CFG_CRC_PRI_FAULT). This cannot be triggered while in configuration mode.

Best regards,

Andy Robles

Hello.

OK, I misunderstand  the CRC SPI functionality.

Is it possible to use the CRC function to secure the SPI communication in Configuration 2 Mode? 
Do you have a example for me how to use the CRC function for all CFG registers?

Best regards
Tobias

Hi, Tobias,

Let us check and see if this is possible.

Best regards,

Don

Hi Tobias,

CRC function can be used to secure communication in the configuration 2 mode amongst other ways.

1. Using the CRC:
   • you can configure the gate driver like you intent to do so while having the MCU run CRC calculations on the SPI commands. To ensure correct communication then you would just write to the CRC_TX register to ensure that the commands you sent into the gate driver were the commands received(Similar to the example in the datasheet).
     • In one of your previous post you mentioned there was a bug in your UCC5870_write_register function. Have you tried re-running your CRC test as in the initial post?
       • We do not have a CRC example code available, but I was able to verify in our lab that writing a random value the CRC_TX bits does in fact trigger a SPI_FAULT. A bug in the write command would explain why the SPI_FAULT wasn't appearing when writing the incorrect value on your side. 
2. Read registers and compare to default values:
   • Another way to ensure you established good SPI communication is to read some registers at start up and ensure you read the default values. Default values for all the registers can be found in the register map section in the UCC5870-Q1 datasheet. For example for CFG2 the default values are 0x0000001000000000 or 0x0200 (Default values for each bit underneath the bit name)
     • 

Let me know if writing to the CRC_TX register works now that the writing function was fixed.

Best regards,

Andy Robles

Hello.

I have fixed my bug at the SPI write function.
I have tried to rerun the example of the datasheet but I don't get any SPI fault at STATUS 2 BIT 11.

    // reset CRC
    ctrl1.all = 0;
    ctrl1.bit.CLR_SPI_CRC = 1;
    ucc5870_write_register( select, OFFSET_CONTROL1, ctrl1.all );

    tx_data.all = 0xFC00;
    crc_calc_data.all = SWAP_UI16(tx_data.all);
    crc = crc8_update( crc, &crc_calc_data.all, 2 );
    msg.ptr_tx_data = tx_data.byte;
    msg.tx_data_size = 2;
    hal_spi_master_transfer_blocking( &mgl_spi_handle[select], &msg, 100 );

    tx_data.all = 0xFA58;
    crc_calc_data.all = SWAP_UI16(tx_data.all);
    crc = crc8_update( crc, &crc_calc_data.all, 2 );
    msg.ptr_tx_data = tx_data.byte;
    msg.tx_data_size = 2;
    hal_spi_master_transfer_blocking( &mgl_spi_handle[select], &msg, 100 );

    tx_data.all = 0xFB2A;
    crc_calc_data.all = SWAP_UI16(tx_data.all);
    crc = crc8_update( crc, &crc_calc_data.all, 2 );
    msg.ptr_tx_data = tx_data.byte;
    msg.tx_data_size = 2;
    hal_spi_master_transfer_blocking( &mgl_spi_handle[select], &msg, 100 );

    tx_data.all = 0xFC13;
    crc_calc_data.all = SWAP_UI16(tx_data.all);
    crc = crc8_update( crc, &crc_calc_data.all, 2 );
    msg.ptr_tx_data = tx_data.byte;
    msg.tx_data_size = 2;
    hal_spi_master_transfer_blocking( &mgl_spi_handle[select], &msg, 100 );

    // check CRC
    tx_data.all = 0xFA30;
    crc_calc_data.all = SWAP_UI16(tx_data.all);
    crc = crc8_update( crc, &crc_calc_data.all, 1 );
    //crc has to be 0x30
    crc = 0xff; // write wrong CRC to get a fault
    tx_data.byte[0] = crc;
    msg.ptr_tx_data = tx_data.byte;
    msg.tx_data_size = 2;
    hal_spi_master_transfer_blocking( &mgl_spi_handle[select], &msg, 100 );

    read = 0;
    ucc5870_read(select, OFFSET_STATUS2, &read);
    //read = 0x4012;

If the SPI check don't work I will try to read and check the registers.
Thanks for your help.