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LM5145: Design and Layout review

Quang LUU
Prodigy 10 points
Part Number: LM5145
Other Parts Discussed in Thread: LM5146,

Hello,

I'm working on a project of building a current profile generator using the LM5145 IC to do the DC/DC conversion from a battery voltage source of 48V to varied output from 3V3/5V-20A to 20V/10A.

I've chosen to use the IC LM5145 from an advice of TI technical support. My design is based on the plurial recommended designs in the LM5145 datasheet and so i chosen to use only 2 Mosfet for switching.

High side : Infineon BSC117N08NS5ATMA1 MOSFET N-CH 80V 49A 8TDSON 11.7mohm 15nC

Low side  Infineon BSC040N08NS5ATMA1 MOSFET N-CH 80V 100A 8TDSON 4mOhm 43nC

Could you please take a look at the layout of the board ?

Best regards,

Quang LUU


Power_Board_V2.3.zip

  • 0
    TI__Guru 60997 points

    Hi Quang,

    This spec is quite similar to the LM5145 EVM (5V/20A/225kHz). Please send a completed quickstart calculator as well: www.ti.com/tool/lm5145design-calc 

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    Thank you for your answer.

    Please find here the completed quickstart calculator.

    1. I'm not sure about the value of ESR for Input and output capacitance since there is no information about them in the datasheet of ceramic capcacitor.

    As of output capacitance, i've used 2 aluminium electrolytics cap of 330uF and 4 ceramic Y5V 10uF. the ESR for 2 paralleled Electrolytic cap is about 100mOhm but with 4 other ceramic cap (relatively low ESR) in parallel, my guess is that the total ESR of output Cap will be reduced alot.

    And Input capacitance is all ceramic Cap with the same trouble of finding their ESR value.

    2. Could you please also explain to me about what have to be payed attention in the choice of the pole and zero for the compensation design ?  the design using the same compensation design that recommended from the Pspice for TI simualtion circuit of LM5145.

    3. My design output purpose is to generate a current profile that vari from 5V-20A to 20V-10A, and the quick start calculator recommend 16.7uH for the 20V-10A output and 3.2uH for the 5V-20A output. So is my choice of 5.6uH inductor corrected ?

    Best regards,

    Quang LUU

    LM(2)5145, LM5146 contorller design tool - revA1 1.xlsm

  • 0 in reply to Quang LUU
    TI__Guru 60997 points

    Hi Quang

    I recommend not using Y5V dielectric capacitors. It should be X7R or X7S.

    The compensation places two zeros near the LC double pole, a pole at the ESR zero and a pole at Fsw/2 -- see the datasheet for more detail.

    5.6uH seems okay, it just results in higher ripple current at 20V out.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Guru 60997 points

    A 1210 ceramic cap is generally 2-3mΩ ESR. I recommend using lower ESR electrolytics as 100mΩ is quite high. Make sure it's a polymer electrolytic that has stable ESR over temperature, otherwise compensation will be very difficult (most aluminum electrolytics have 5x nominal ESR at cold).

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hi Tim,

    Thank you for your advice. Indeed, i've replaced and use the X7R cap ceramic for the latest version of design. For the electrolytic Cap, i'll see if we can use another one.

    What i'm more concerning now  is the layout of the board, have you take a look at it ? Did i missed any vital point in the layout? Do you have any advice in layout of this circuit ?

    Best regards,

    Quang LUU 

  • 0 in reply to Quang LUU
    TI__Guru 60997 points

    HI Quang, I'll take a look now. In general, I recommend following the LM5145 and LM5146 EVM designs as closely as possible. For power stage layout guidance, see app note SNVA803.

    --

    Tim 

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hi Tim,

    Have you take a look at my board layout ?
    Per comparison with the reference document, i've placed the MOSFET to minimize the power Loop area and near the input capacitor to decoupling of high switching frequency.

    I wonder if the position of the output capacitors are ok ? also for the position of the feedback resistor network.

    Regards,

    Quang LUU 

  • 0 in reply to Quang LUU
    TI__Mastermind 22299 points

    Hi Quang,

    Tim is out on vacation, please give me a few days to catch up and respond to this.

    -Orlando

  • +1 in reply to Orlando Murray
    TI__Mastermind 22299 points

    Hi Quang Luu,

    Your layout placement is good.

    The output capacitors placement is good too.

    The feedback resistor placement is not good. The lower feedback resistor R61 should be right next to FB pin and AGND pin. Consider using smaller footprint components to get closer to the IC.

    I don't recommend using thermal relief connections for polygons.

    You need the LM5145 IC GND DAP to completely pour onto the main GND plane so the GND plane is an effective heatsink.

    The same for D11, Q5, and Q6, the FETs need to completely pour into the polygons so the top layer copper can be a good heatsink.

    The inductor L5 should also not use thermal relief polygon connection.

    See LM5145EVM-HD-20A EVM layout files for how the FETs and IC are poured to planes.
    Also reference how the FB resistors and compensation network are placed.

    Hope this helps, let me know if you have further questions.

    -Orlando