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UCC28950: SYNC function

user6225074
Prodigy 30 points
Part Number: UCC28950

We are using UCC28950 in Slave mode.

There is a problem that the timing of the falling edge of the SYNC pin and the gate output sometimes shift.

If it is operating normally, it is considered that the falling edge of the SYNC pin and the internal CLK are synchronized,

and then OUT-A and B are output. However, sometimes OUT-A and B are output before the falling edge.

I think it is the effect of noise on the SYNC pin, and I am thinking of connecting a CR filter.

So, please tell me the following.

1. Is there a recommended slew rate for the falling edge?

2. Is there an upper limit to the capacitor capacity that can be connected?

Thank you.

  • 0
    TI__Guru* 85616 points

    Hello,

    Make sure the frequency of the slave is set to 80% of the master.  You always sync the slower frequency to the faster frequency.

    Also make sure that the RT resistor is set correctly and the SS pin has an 825k ohm resistor tied to it and ground.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 140 points

    Hi Mike

    Where in the datasheet is it stated that the frequency of the slave should be 80% or less of the master?

    On the data sheet, "the SYNC frequency must be greater than or equal to 1.8 times the converter frequency.", But I don't think it matches.

  • 0 in reply to user6304160
    TI__Guru* 85616 points

    Hello,

    The primary frequency is 1/2 the sync frequency.  1.8/2 would be 90% slower than the master.  I have always used 80% as a rule of thumb.  It appears that the other of the data sheet used 90%.

    Regards,