TPS929120-Q1: Clearing Faults to default

Hi Jacques,

Please help to check the following 2 items:

1. Has the open-circuit been recovered at the time the fault is being clear?
2. Is bit CONF_CLRLOCK in register CONF_LOCK (address 0x61) set to 0x0?

Best Regards,

Ben

Hey Ben,

For your questions:

• The condition has been cleared
• CONF_CLRLOCK is set to 0x00 (in fact, address 0x61 is set to 0x00)

Best,

jacques

Hi Jacques,

Next step is to read registers FLAG0 (address 0x70) and FLAG1 (address 0x71)

1. Before the open-circuit happens
2. After the open-circuit has been recovered and 0x07 was written to address 0x60.

Best Regards,

Ben

Hello Ben,

This has taken place. The flags are not cleared after 0x07 is written to 0x60. The only action that recovers and clears the flag is writing 0x10 to 0x60 for a re-load of registers.

-Jacques

Hi Jacques,

Writing 0x07 to 0x60 should be able to clear the open-circuit fault. Before the fault occurs, all bits in FLAG0 and FLAG1 are 0. After the open-circuit fault, FLAG0 becomes 0x11. Then writing 0x07 to 0x60 will make FLAG0 0x00 again. You can see this in below waveform.

Best Regards,

Ben

Hey Ben,

Above is what is expected, but is not happening in this case. It has also been observed that RSVD registers that are read only are being set, such as register 0x56 being set to 0xA0. Any ideas why a read-only RSVD register that should be 0 is set to 1? 

-Jacques

Hi Jacques,

Please ask the customer to obtain above waveform of RX and TX-pins when they try to clear the FAULT.

Best Regards,

Ben