TPS7A63-Q1: W_FLT Pin responds

Hi Frank,

1. nWD_EN Pin keeps LOW, WD Pin keeps LOW as well, how should WD_FLT Pin responds under this condition?
   1. Assuming you Enable the watchdog and don't service it the WD_FLT pin should remain at the voltage it is pulled up to until the Open window time expires once this time expires the WD_FLT should go low.

2. nWD_EN Pin is HIGH at first(turn to LOW 2s after power on), WD Pin keeps LOW all the time, how should WD_FLT Pin responds under this condition?

   1. The FLT pin should stay pulled up high until the open watchdog period expires which wild be 2s +8*twd. Once this expires the FLT pin should pull low.

The other thing to keep in mind here is that there is also some dependency on the nRST pin, so you will need to provide the conditions of that pin as well. My answers above all assume the NRST pin has gone high already.

Regards,

Mark

Mark.

Thanks for your reply.

Rosc=10k, so we got the tWD=10e-2 s.

Below is the osc waveform we catched. 

Blue=nRST,

Yellow=nWD_EN,

Green=WD,

Pink=WD_FLT.

As far as we think, the WD_FLT should be pull LOW. Bur we see it is always HIGH from the waveform. Do you have any idea so we can figure out the problem?

BR

Frank

Hi Frank,

Can you share the schematic for TPS7A63-Q1?

Thanks!

Mark

Mark,

Please refer the attached sch.

BR

Frank

Thanks Frank!

I don't see anything wrong with this right now. I will take a look at this on the bench tomorrow. Can you have them try to swap the part to make sure that this is an issue with more than one LDO?

Regards,

Mark