TPS7A85A: Affect of Cff

Hi Hirotsugu, 

Typically, Cff helps improve the transient performance of the device. Can you share the schematic and possibly, a scope shot showing the described behavior? 

Best, 

Edgar Acosta

Hi Edgar-san,

I attach the schematic and scope shot.

I am using a DAC to make it a variable power supply.

At the setting of 1.25Vout, if Cnr is 10nF, the voltage drops by 20mV, and if it is 100nF, the voltage drops by about 40mV at 1.7A load, and VFB is lower than 0.8V.

What is the root cause?

Best Regards,TPS7A85A.pptx

Hi Kobayashi-San,

Have you tested this without the Cff cap?

Is it possible to do the same test without the DAC and adjusting the FB network to get 1.25Vout, a 21.5kOhms should be sufficient. 

If we look at the FB without counting the DAC: 

Vout=0.8*(1+12.1k/6.81k)= 2.221V

Or, is there a way to tap the ANY OUT pins to adjust VOUT to 1.25V and do the same test? 

It could be that the interaction between the DAC and the FB might be shifting the value once the device is loaded. Let me know if testing without the DAC is doable. 

Best, 

Edgar Acosta

Hi Edgar-san,

I'm not thinking of measuring without a DAC because it's an application that requires adjusting the output voltage.

I will try to measure without Cff.

Best Regards,

Hi Kobayashi-San, 

I understand. Doing a test without the DAC will help us rule out if there is or not an impact of using the DAC, and will provide more insight to help us narrow down the root cause, but not to eliminate the DAC from the application. 

Let me know how the results look without Cff. 

Best,

Edgar Acosta

Hi Edgar-san,

This problem is occurring on a new board.

The difference from the previous board and the result by capacity of Cff are attached.
 TPS7A85A is used on a new board.
 Cnr and Cff are changed for lower noise.

The measurement is still using the DAC.
Is there any possible cause?

Best Regards,

Hi Kobayashi-San, 

Thank you for sharing the table. When looking at the table, it caught our attention that the first line with the CFF cap is different, notice how the rest of the lines follow the same trend. 

This leads to suspect that perhaps the LDO, CFF or the DAC could've been damaged. 

Furthermore, while analyzing the circuit, is there a control loop for the DAC?

We understand that the DAC is part of the application, is it possible to only remove R801? This will isolate the DAC and LDO, and with the given resistor values, there is already an expected ~1.25V at the output. In a worst case, we would expect a load regulation of 0.08mV/A, which is ~136uV. Therefore, isolating both components will give us more insight of what is occurring. 

Best, 

Edgar Acosta

Hi Edgar-san,

I updated the table.

I changed the IC, Cnr/ss and Cff on the new board.

I suspected the effect of Cff and reduced the capacity, but the Load Regulation did not improve.

I'll try it without DAC, but does Cnr/ss have any effect?

Best Regards,

Hi Kobayashi-San, 

Cnrss and Cff should not have any DC performance impact. 

Cnrss would change the ramp rate for Vout and help improve the noise performance. 

As to Cff, it should help improve the PSRR and as well some of its AC performance. It could affect the DC if there is a leakage or if the capacitor is damaged. 

We have an application note for Voltage margining that implies the use of a DAC. The app note goes through the math to properly size R3 for a +-10% Vout margin, in this case it would be R801. We also have a video of how to use a DAC for margining: Voltage Regulator Margining. This video also talks when there is a load present.

Notice how your bottom resistor is lower than the top R, therefore, once the device is loaded, the interaction with the DAC might be causing some voltage drop, specially if there no control loop for the DAC to take into account any of the changes happening at the output of the LDO. 

I went through some math based on some of the data provided and some of the things discussed in the app note and video.

Assuming the DAC is a 0V to 5V DAC and making R2=50kOhms, from 1.6V to 1.2V there is a margin of 0.4V. I also took 1.25V being the nominal output voltage for this application. After going through the math, R1 and R3 should be 36.6kOhms and 457.8kOhms respectively. 

Best, 

Edgar Acosta

Hi Edgar-san,

We tested it without a DAC and as a result, there was no voltage drop.
I am reviewing the resistance value and have a question.
Does R2 need a resistance value of around 50kΩ?
As another point to note, should I set R1> R2?

Best Regards,

Hi Kobayashi-San, 

The value for R2 does not have to be 50kOhms. The 50kOhms is only an example and was used for simplicity and being consistent with the example in:  Voltage Regulator Margining

To the question of R1>R2, this will depend on design approach. Notice how for the 50kOhm use case R2>R1, however, if R1 is chosen first using the following equations and the example from the App Note:

then one could end with R1>R2:

Lets assume that R1 is kept to be 12.1kOhms, then Inominal would need to be ~37uA giving us an R2 value of 21.5 kOhms. This will be very application dependent.

You can find the app note here : Voltage Margining and Scaling Circuit with a Voltage Output Smart DAC. 

Best, 

Edgar Acosta