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TPS6594-Q1: PMIC Reset Reasons

Lakshmi Shetty
Prodigy 205 points
Part Number: TPS6594-Q1
Other Parts Discussed in Thread: TDA4VM, , DRA829

I am using TDA4VM Eval board and TI SDK 8.2.

I need to understand the possible reasons for PMIC reset.

What and all registers I need to read and store in NVM, to get the previous reset reason.

Note: I am referring TPS6594-q1 data sheet.

Thanks in advance,

Lakshmi Shetty

  • 0
    TI__Mastermind 25725 points

    Hello Lakshmi,

    The interrupt registers (0x5A to 0x6C) hold their value as long as VCCA  doesn't drop below 2.7V. Therefore, if only the PMICs and the discrete components they monitor/control are reset due to a fault, the interrupt registers will store that cause. Please note that these interrupts are "Write to Clear", so it they won't just tell you the reason for the last reset if multiple resets happen in a row.

    -Mike

  • 0 in reply to Michael Gambrill
    Prodigy 205 points

    Hello Michael,

    Thank you so much for your reply.

    By this interrupt register values we can identify the reason behind the reset.

    Is it possible to generate any of this interrupt in R5 and verify. Is there any reference code?

    Thanks in advance,

    Lakshmi  Shetty

  • 0 in reply to Lakshmi Shetty
    TI__Mastermind 25725 points

    Hello Lakshmi,

    I am looping in another engineer more familiar with the SDK and he will better able to answer your question

    -Mike

  • 0 in reply to Michael Gambrill
    TI__Guru 64491 points

    Hello Lakshmi,

        Can you clarify if the reset is a cold(power removed from TDA4) or warm reset(PORZ is pulled low then high)?

        As Mike mentioned you can use the interrupt hierarchy to determine the source of the interrupt.  This is part of the PMIC low level drivers.  You can also find a more specific description of the fault and triggers in the user guide.

        Most of the interrupt sources are hardware based (under and over voltage of rails).  The Error Signal Monitor and Watchdog could be used to generate an interrupt but be advised that the default setting is a warm reset in the event of this type of error.

    Regards,

    Chris

  • 0 in reply to Chris Sterzik
    Prodigy 205 points

    Thank you Michael and Chris.

    I am interested in reasons for warm reset. As per the data sheet, below interrupts will trigger warm reset.

    ESM_SOC_RST_INT
    ESM_MCU_RST_INT
    WD_RST_INT
    WD_LONGWIN_TIMEOUT_INT

    So, by checking these interrupt status will give the reset reason. Is my understanding is correct?

    Thanks in advance,

    Lakshmi Shetty

  • 0 in reply to Lakshmi Shetty
    TI__Guru 64491 points

    Hello Lakshmi,

    Please be advised that the datasheet provides an example implementation which does not exactly reflect the implementation with DRA829.  For example the ESM_SOC_ERROR only pulls H_SOC_PORz_1V8 low and then high while the ESM_MCU_ERROR and WD_ERROR pull both H_SOC and H_MCU when in the ACTIVE mode.  Please refer to the user guide for a complete description of the signals and the error triggers.

    Lakshmi Shetty said:
    So, by checking these interrupt status will give the reset reason. Is my understanding is correct?

    You are correct.  The interrupts are provided in a hierarchy.  So at the top level you might see the WD_INT but if you drill down you will see if the specific error was related to an answer being too early or an answer being incorrect (see WD_ERR_STATUS).

    If you are troubleshooting, then I would look into the WD_LONGWIN_TIMEOUT_INT.  GPIO8 of the primary pmic is configured as the DISABLE_WD and should be pulled high when nRSTOUT(PORz) is released.  If this is not pulled high, then the processor must service the WDOG before the long window expires.  

    Regards,

    Chris