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TPS78233 Ground Plane Recommendations to improve PSSR and Noise

Russ Ramsay
Prodigy 460 points

I am designing in a TPS78233 and have a question about the "board layout recommendations to improve PSSR and noise performance" provided on page 10 of the datasheet. How much does the separate ground plane improve performance? There is only one CPLD that is being powered by the output of the TPS78233 so I'm wondering if a single ground plane is sufficient.

Also, in the "internal current limit" section, there is a discussion about external limiting of output current. Is there a suggested implementation that you can provide? We do not intend to have the output exceed the input voltage. The only condition would be an error/defective circuit card.

  • 0
    TI__Expert 8890 points

     

    Hello Russ,

    There could be a 2dB improvement in PSRR if the layout were configured as described. These measures are usually not taken unless PSRR is very important to the application. Applications involving digital circuitry will see very little advantage to employing a split ground plane as described.  My best recommendation would be only to locate your input and output capacitors very near to the IC's pins and (because I am overly conservative in my design approach) to double the amount of recommended capacitance - both for derating purposes and to optimize transient responses.

    Regards

    Bill

  • 0 in reply to Bill Stokes
    TI__Prodigy 460 points

    Bill,

    Thanks.  Feedback is that this answers the ground plane question exactly.

    Any recommendations on an available reference design for limiting the output current?

    -Russ

  • 0 in reply to Russ Ramsay
    TI__Expert 8890 points

     

    Hi Russ,

    Sorry about that.  This particular LDO has a forward current limit, operational during normal operation when Vin > Vout, of 230mA (typical); but, has no reverse current limit protection when the Vout > Vin. This latter condition occurs because the output then forward biases the body diode of the main pass-FET-transistor.  As you say, since your application never experiences this condition there is nothing to worry about.  Mostly the concern arises if there is some prebias voltage charge to Vout while the Vin is connected to ground (during turnoff).   We usually recommend that a schottky diode be placed in series with the IN pin to block reverse current flow.

    Regards

    Bill