Hi
I am using a threshold level of 2.63 to check my VDD of 3.0V. The circuit is as follows:
When 3.0V is present, the RESET level drops to 0.325V. When 3.0V is not present RESET level rises to 0.545V. Both cases the FET reverses the state to a logic high.. I increased the pullup resistor to the 3.3V to 51k and the RESET level drops but the RESET level does not go to open circuit when VDD =0. The input capacitance of the n-FET is 73pF typ. Any ideas?