Current sinking capability of CHG and DSG pins
This is a snippet from the schematic given the multiple MOSFET application guide. www.ti.com/.../sluaa09
The transistor highlighted and the gate resistance is to be selected based on the gate current from the CHG driver. In our implementation we have 6 MOSFETS in parallel and the total gate capacitance is 68x6 nC.
Kindly recommend a procedure to estimate the applicable DSG currents/switching time for the MOSFETS within the rated limits of the BMS IC.
Maximum current sinking capability of CHG and DSG pins are not directly specified in the datasheet.
