In datasheet,it said that:"One solution to this issue is to ramp the voltage up to the target without synchronous rectification (SR), and then to activate SR after the voltage is regulated. When activating or deactivating
SR, in order to avoid glitches in the regulated voltage, it is best to gradually increase/decrease the Sync FET on-time."
About the operation , I have some question:
1. If use front end2 to ramp up, How to set the value of RAMPDACEND.RAMP_DAC_VALUE? the output target voltage?
2. only accomplish SR soft on, it need to enable the bit of IDE_DUTY_B_EN in DPWMCTRL2?