TPS61378-Q1: Pgood Trip Point Clarification

David Shumate

Part Number: TPS61378-Q1

Team,

Can you help clarify worst case Pgood set and trip points for the TPS61378?

1. In the datasheet I see that Pgood sets at 90% but then has a 5% hysterisis. Does this mean after Pgood is high we need to be at 85% to drop low again. (Assuming 5V0 out then Vout would need to be 5.0*0.85=4.25V to drop)

2. The values in the datasheet are just shown as nominal, what are the min and max values for VPG_TH and VPG_HYS:

Best,

David

over 3 years ago

0 Zack Liu over 3 years ago

TI__Mastermind 34231 points

Hi David,

Thank you for reaching out. Please see my comments below:

1. Yes, your understanding is correct.

2. For further information, we could discuss it via email.

0 Mayunthan Nithiyanantham over 3 years ago

Intellectual 785 points

Hi,

In order to monitor the undervoltage and ensure that the CAN Transceiver does not go beyond its known tolerance, we plan to use GPIO8 of the HERA PMIC to a voltage divider VDD_5V0 for monitoring . In which case, we won't be using the SPMI_SCLK & SPMI_SDATA. Before we can implement this, I'd like to know whether or not SPMI_SCLK and SPMI_SDATA can contribute to a faster bootup timing?

0 David Shumate over 3 years ago in reply to Mayunthan Nithiyanantham

TI__Expert 7975 points

Hi Mayunthan,

Note this thread was specifically for TPS61378 Pgood question. You'll need to create a new post with LP8764 as the part number to make sure questions get mapped to the right team member.

I will, however, reply directly to the email you sent me to answer the question.

Best,

David

0 Mayunthan Nithiyanantham over 3 years ago in reply to David Shumate

Intellectual 785 points

Hi David,

I will create a new post if I have additional questions on LP8764.
Thanks so much for the email response.

Best Regards,
Mayunthan

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TPS61378-Q1: Pgood Trip Point Clarification