UCC28950: Irregular C, D drive output

Hello,

I found these threads on the e2e explaining what you are seeing and what is causing it.  The information in these threads should help you understand the operation that you are seeing in your design.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/817030/ucc28950-asymmetric-duty-cycle-operation

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/274735/ucc28950-mismatched-c-d-outputs

Regards,

Hello,

The UCC2895 issue seemed to be due to light load startup and not having enough PWM signal.  However, the controller in that situation was trying to demand 0% duty cycle.  To resolve this issue they recommend adding a ramp to the CS signal per application note slua275.  The following link will bring this to an application note describing the issue and how to resolve it.  https://www.ti.com/lit/an/slua275/slua275.pdf

The UCC28950 will sync out A and B to the master clock and phase shift out C and D to control the duty cycle.  When the controller demands 0% duty cycle it will phase shift out C and D 180 degrees.  This will make OUT C and D's pulses look twice as large as they should be.  This is normal and is what this waveform that you took is showing.

In your waveform what looks like occurred is duty cycle jumped form 60% to 100%.  The converter then demanded 0% duty cycle and recovered slowly.  It is almost as if over current protection kicked in and discharged the soft start capacitor.  You can confirm this by looking at SS and comp when this occurs.

The UCC28950 when operating over 90% duty cycle can trigger over current protection earlier than it should.  This was corrected in the UCC28951 and is recommended in designs that require duty cycles of greater than 90%.  The following link will bring you to an application note that explains that behavior.  https://www.ti.com/lit/pdf/slua853

If your design requires greater than 90% duty cycle you should be using the UCC28951 instead of the UCC28950.

Regards,

Hello,

You had asked if the UCC2895 had the same issue as the UCC28950.  So the following information describes the UCC2895 issue and the UCC28950 full load behavior that you are observing.

"The UCC2895 issue seemed to be due to light load startup and not having enough PWM signal.  However, the controller in that situation was trying to demand 0% duty cycle.  To resolve this issue they recommend adding a ramp to the CS signal per application note slua275.  The following link will bring this to an application note describing the issue and how to resolve it.  https://www.ti.com/lit/an/slua275/slua275.pdf

The UCC28950 will sync out A and B to the master clock and phase shift out C and D to control the duty cycle.  When the controller demands 0% duty cycle it will phase shift out C and D 180 degrees.  This will make OUT C and D's pulses look twice as large as they should be.  This is normal and is what this waveform that you took is showing.

In your waveform what looks like occurred is duty cycle jumped form 60% to 100%.  The converter then demanded 0% duty cycle and recovered slowly.  It is almost as if over current protection kicked in and discharged the soft start capacitor.  You can confirm this by looking at SS and comp when this occurs.

The UCC28950 when operating over 90% duty cycle can trigger over current protection earlier than it should.  This was corrected in the UCC28951 and is recommended in designs that require duty cycles of greater than 90%.  The following link will bring you to an application note that explains that behavior.  https://www.ti.com/lit/pdf/slua853"

The over current protection is triggered when the slope compensation ramp + the CS signal reaches 2 V.  This can be seen in the block diagram of the data sheet.

1. You can change the trip point by adjust the current sense resistor and/or adjusting the slope compensation.

It appears that you are using the UCC28950 over 90% duty cycle.  It is recommend per application note slua853 that you use the UCC28951 in applications where over 90% duty is required in your design.

Regards,

Hello,

1a. The UCC3895, UCC2895, UCC1895 are the same device with different thermal characteristic, see the ratings below.

1b.  The UCC28950 is one device rated for one teampature range please see below.

Please note this waveform you provided the CS signal does not seem present (CH3) it just looks like noise. 

If you are using the UCC28950 I would have thought it was due to the OCP condition.  However, you verified it in the UCC28951.  So it is not that.

I looked up the issue and was a glitch circled below.  

When the slope compensation + the CS and slope compensation is greater than 2 V it will start to discharge SS and demand zero duty cycle.  It will cause both C and D to phase shift and the period will look twice as long.  This will occur in both the UCC28950 and UCC28951.  The only difference is the glitch circled above in the UCC28950.

What you are seeing is normal behavior for the UCC28950 demanding zero duty cycle.  This waveform you took below shows the converter is demanding max duty cycle and then shifts C and D to demand 0% duty cycle.  It looks like the design may have hit an OCP condition and discharged SS demanding 0% duty cycle and then started recharging soft start.

Original I thought it was the glitch issue because you were using the UCC28950.  However, that was not observed in your waveforms.  

It just seems that you are seeing normal behavior when the UCC28950 or UCC28951 behavior.  The devices are doing what they were design to do.

Regards,

Hello,

Please see below.

1.Is it possible to operate at 0% duty even if SS is not pulled out?

>Yes this would be demanded by the voltage amplifier.

>In your scope plots for SS and COMP you have them set for AC, you might want to retake these with these channels set on DC.  You will not see gradual changes in DC voltage with an AC setting.

2.When the glitch you told me about occurs, does it always turn off for a short period of time?

>If it occurs that is correct.

>I am not seeing the glitch on your plots.

3. How does the 28951 deal with glitches?

>This was changed with a metal mask change to remove the condition in the IC.  The details are proprietary. 

You had mentioned that CH3 is SS in the following image.  The scope is set on AC for CH3 so you may not see the SS discharge..  Could you reset CH3 to DC and retake the plot.

Regards,

Hello,

Your waveform looks to be steady state at 3.7V.  After soft start this should have charged up to 4.65V.   Is there something in your design preventing SS from reaching 4.75V? 

Maybe your SS voltage be clamped at 3.7V is causing the issue.  Please allow the SS to charge to 4.65V to see if the issue goes away.

Your comp is at 2.4V demanding maximum duty cycle and controlling the peak current to 1V.  Then the peak current jumps to 1.25V.  If Comp did not change then the device should demand 0% duty cycle when this occurs.  Because it is above the control voltage.  The below waveforms looks like this is what the device is doing.

.

If the comp was steady when the below waveform was taken the UCC28950 should not have asked for more duty cycle.  Did this waveform look the same for the UCC28951.  I am just curious?

The behavior reported for over 100% duty cycle for the UCC28950 glitch may cause the current to jump.  However, I did not see the glitch in your above waveform.  However it is demanding more than 90% duty cycle and this is a known issue in the UCC28950 if the duty cycle is over 100%.  You may not just be seeing it because you scope is bandwidth limited. You may want to reevaluate without bandwidth limiting.

Regards,

Hello,

Please see my comments below.

1.Regarding the SS voltage clamped to 3.7V, after startup, it is set to 4.65V, but after the problem occurred, it has stabilized at about 3.7V.

>This should stay at 4.65V unless an over current condition has occurred.

>Can you share a schematic?

>Can you separate these three plots with better resolution.  I can't see them clarely. 

Please see below.

CH1:COMP, CH2:Transformer Current, CH3:SS,  CH4:OUTD

Is it correct to assume that the SS pin is pulled out while the OCP is being detected, and that it is not pulled out when the CS peak voltage is lower than the OCP threshold? Looking at the waveform above, I don't think the OCP is continuing because the transformer current doesn't change before and after SS is clamped to 3.7V. I wonder why the SS voltage has not returned to 4.65V. 

>According to the block diagram the OCP threshold is the sum of the CS signal and slope compensation.

>What is your slope + CS signal?

This is unintended behavior, but since the problem also occurs when the SS is running at 4.65V, the initial cause of the problem is likely elsewhere.

>The SS being discharged to 3.7 V indicates that OCP is being detected or is being loaded down by an external source.

>I am curious do you have a resistor tied from VREF or any other external source to the SS pin preventing it from discharging?

2. I don't think it's turned on twice by requiring 0% and 100% duty for control. Even if 0% is requested as you say, I don't know what caused the previous mode not to turn off.

>You claimed that COMP and SS are stable and the devices peak current goes larger than it should.  The controller should demand 0% duty cycle when this occurs.

One of the reasons why I don't think it's due to duty control is that there are cases where the On continues longer than twice as shown in the waveform below. If it continues to be ON, it will operate like a 0% duty, so the output will drop and it is requested to increase the duty.

>In this waveform you can see the peak currents are control to a different voltage than the Comp demands.  The first time it occurs it looks like it is demanding 0% duty cycle and misses a switching cycle.  The next switching cycle the CS signal is even higher and the transformer looks slightly saturated and the next pulse is missed.  Once again 0% duty cycle is being demanded.

>Your controller appears to be operating greater than 90% duty cycle and in OCP.  This will cause a glitch and extended off time in the UCC28950, which was supposed to be resolved in the UCC28951.  You should be using the UCC28951 in your design.  I know that you claim it had not resolved your issue, but you should still be using it.  You also need to figure out why the SS pin being discharged to 3.7V.  Could you please share your schematic for review?

3. I've checked without any bandwidth restrictions to see if there are any glitches. Glitch could not be detected even if the capacitor for noise elimination of OUTC and D was additionally removed.

>Thankyou for doing this and I can see the glitch is not observed.

>You can see the CS signal in the transformer has increased before this occurred.  It should not if the COMP and SS is stable.  It should try to control it to the same level.  Is there a shift in the output load when this occurs?

>This does appear to be asking for 0% duty cycle.  The C and D are shifted 180 degrees and the waveform will look like this when it occurs.  The other e2e links previously shared discuss similar behaviors to this.

4. We have confirmed that adding resistors in series to OUTC and D or reducing the switching noise of the PFC circuit reduces the frequency of occurrence of this problem. I believe the problem is caused by noise. Please let me know which pin the noise can cause this problem

>Noise could be contributing to the issue.  Adding resistors as you have done will dampen ringing.

>Using filtering capacitors on critical pins such as CS will help.

>If you are using the device in slave mode please make sure you have an 825 k ohm resistor tied between SS and ground.  This is mentioned in the data sheet.  If this is not done the device could also misbehave.

Regards,

Hello,

You mention that if your design does not have a 825 k ohm resistor from SS pulled to ground that you do not see the issue.  Please note that the 825 k ohm resistor from the SS pin to ground is only required if you are using the device in slave mode.  If you are using it as a master controller this resistance is not required.

Regards,

Hello,

The commend about the 825 k resistor from SS to ground only being needed in slave mode is written on page 18 of the data sheet.

A copy of the page is below.

Your questions are related to the C and D gate drive's known behavior.  It is not a device malfunction. The C and D will phase shift to produce 0% duty cycle.  This behavior has been documented on the e2e. Your questions were related to this behavior and were previously discussed in this thread.  However, I have found this thread that discussed this issue as well.  You may find it helpful in understanding the C and D behavior.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/817030/ucc28950-asymmetric-duty-cycle-operation

If you are using the UCC28950 in slave mode you will require the 825 k ohm resistor from the SS pin to ground.  There is most likely something in your design that is preventing SS from being charged to 4.65V.  I know it is not possible to share your schematic.  However, the following link will bring you to an application note that you can use to check your schematic.  https://www.ti.com/lit/pdf/slua560

Regards,

Hello,

Please see below.

Q1.I don't think it's possible for the waveform to just operate at 0% duty, but can you explain it?

You say this is known behavior, is that true? Please see below.

>This is correct.

>Think of pulse demanding a 100% duty cycle and the next cycle demanding 0%.

1.) 100% duty cycle A and D on, C and B off

2.) 0%  B and D on, A and C off, This make it look like the C and D pulse has twice the period.  What happen is phase C and D shifted 180 degrees.

>This is  what you are seeing here.  You were in a 100% duty cycle.  The current is higher then the comp voltage demands.  The next duty cycle should be zero %.  This is what the controller is doing.

Q2.It is clear that noise is the culprit. I've heard this many times, but please tell me which pins can cause this behavior when noise enters and why.

>You are correct noise can cause the controller to misbehave. 

a.) If you have this issue you should be able to remove it with filtering.

>Any pin being pulled below ground could cause the circuit to misbehave as well. 

b.) If you have this issue, you should be able to resolve it with Schottky diodes.

Q3.Is 800kohm acceptable for the SS pin resistance? What problems, if any, can occur?

> The 825 k ohm resistor was supposed to be used to keep the device from entering an IC design test mode, when the device is being used as a slave device.   Using a lower value should just steel slightly more soft start current.  I would not think it would be an issue by using 800 k ohms of resistance.

Iss = 25 uA - 3.7V/825k = 20.52 uA

Iss =  25uA - 3.7V/800k = 20.37 uA

You might run into problems if you used a resistor that was so small that it stole all of the SS current.

Regards,

Hello,

I have added comments directly to your waveform to help explain what is happening.  Your peak current becomes higher than what the voltage amplifier is demanding and then the converter phase shifts C and D 180 degrees to demand 0 duty cycle. 

To help with out this works.  I have edited the C and D waveforms to show you what a 178 degree phase shift in the C and D pulses would like.

Q1. I believe the timing for C and D is correct for the peak current that is being seen on the transformer.  The peak current for some reason went higher than the control voltage and the controller is trying to demand 0% duty cycle.

Q2.  I have seen your plots showing that SS and Comp voltage has not changed.  So why is the current climbing when it should not.  Why for that one switching cycle does the controller demand 100% duty cycle and increase the current beyond the controlled current? 

Why were you asking about the 800 k ohm resistor on the SS pin?  Did this remove your issue?

Regards,

Hello,

You are correct that A will not turn on if B is on.

The device is capable of 100% duty cycle.  So you are not correct about the D operation if zero duty cycle is demanded after 100% duty cycle.  If the duty cycle is less than 100% you are correct.

If A and D are on they demand a 100 % duty cycle.  If at the very begging of C and B cycle.  If Zero duty cycle is demanded, which is what you are seeing.  It will force B low and D high.  In your case since the device went to 100% duty with A and D.  When B went high D also went high to demand zero duty cycle based on what the CS signal is seeing.

I know you cannot share your schematic.  I looked at your CS signal from previous posts and it looks it quite noisy.   Maybe it is the noise on the CS signal that is causing the design to go to 100% duty cycle.  Have you tried filtering the CS pin.  1 k ohm and 22 pf of the CS resistor will generally due the trick.

Your current sense signal also shows noise going more than 500 mV below ground.  If this noise is truly on the CS pin it will cause the device to misbehave.  This is because negative voltage breaks down the isolation of the silicon.  All pins should not gore more than 300 mV below ground to prevent this from happening.  Filtering should help with this and adding a Shottky diode across CS and Gnd would help here as well.

If you are using the SR FETs I would recommend turning them off before critical conduction so there is not reverse current in the FETs.  This can be done with a voltage divider off a VREF to the DCM pin.  If this is not done the FETs could be damaged at turnoff and the CS signal could be affected by this reverse current.

When it comes to the CS transformer it needs to be before the H-Bridge and not in series with the transformer.   Some customer's have made the mistake of putting the CS transformer in series with the transformer.  If the current sense transformer is in series with transformer the DC information could be lost.

I would also check your current sense transformer to make sure it is being reset correctly.   If it is saturating it will also cause issues.

The following link will bring you to an application note that discuss how to set up the current sense transformer and how to turn off the SR FETs before critical conduction.  You may find this information helpful.

https://www.ti.com/lit/pdf/slua560

Regards,