Other Parts Discussed in Thread: TPS546D24A
Hello,
My customer has a few inquiries about the TPSM8D6C24 design along with a circuit review.
Please review the attached file below.
TI_TPSM8D6C24_design_review.pptx
Thank you.
JH
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello,
My customer has a few inquiries about the TPSM8D6C24 design along with a circuit review.
Please review the attached file below.
TI_TPSM8D6C24_design_review.pptx
Thank you.
JH
Hi JH,
Our US team will review it and reply you by next Monday.
As VSET resistor values to get 0.85V output, is it possible to use both methods below?
Is there more recommended values?
Yes, both resistor combinations will select 0.85V and they are functionally identical. The single 17.8kΩ resistor to AGND is generally preferred.
What is the difference between IOUT_OC_WARN and IOUT_OC_FAULT?
IOUT_OC_WARN will trigger an SMB_ALERT low and set the IOUT_OC_WARN status bit in STATUS_IOUT but will not affect operation
IOUT_OC_FAULT will trigger an SMB_ALERT low and set the IOUT_OC_FAULT status bit in STATUS_OUT. If IOUT_OC_FAULT_RESPONSE is set to shutdown (default) this will also shutdown operation of the output and restart or latch-off per the restart selection of IOUT_OC_FAULT_RESPONSE (Default is restart with infinite hiccup attempts)
Is this a typo? Isn’t OC_WARN (A)/OC_FAULT (A) correct?
Yes, the numbers are listed in the Order WARN / FAULT
Iout=40A : There is no effect on the output, only the alarm can be read through the IOUT_OC_WARN_LIMIT Register.
Iout=52A : IOUT_OC_FAULT Shutdown blocked output.
Yes, through the response to a fault depends on the setting of IOUT_OC_FAULT_RESPONSE, which can be set to Shutdown, Delayed Shutdown, or Continue Operating without Interruption.
The contents of “short to GND” are different between Table 5-1 and Table 7-5.
Where should the pin below be connected, PGND or AGND?
MSEL1, MSEL2, ADRSEL, VSEL, PGOOD
Tables 5-1 and Tables 7-5 are discussing different things.
The Loop Follower connections in 7-5 recommends connecting unused pins to PGND, which can be the system ground plane to ease routing since these pins are not used by the converter in this programming state. Since the device ignores the values on these pins, the ground they are connected to does not need to be as accurate as when the pins are being used. They can also be AGND without issue.
Table 5-1 describes the connection of the pins when the pins are actively used by the device, in which case they should be connected to AGND.
If there is a parameter calculation file of the TPSM8D6C24, please share it.
There is not one available yet, but you can use the TPS546D24A calculator tool and select a 220nH inductor with 80% derating
Could you please provide performance data such as thermal, efficiency for 4-phase application?
I will need to check to see what we have available.
For the schematic review, I still need to check the compensation and the pin-strap, but otherwise things look good.
I am a little concerned about the power dissipation for an 1005 (0402) snubber resistor on a 550kHz switching frequency and 1nF snubber capacitor. I calculate 80mW of power dissipation (12V^2 x 1nF x 550kHz) and a typical 1005 (0402) resistor is only rated for 62mW power dissipation.
Also, it looks like you selected 1608 (0603) resistor for pin programming, which do not require power dissipation, so some size could be improved with 1005 resistors. Additionally, for a 4-phase design, many of these resistors are not needed and space could be saved by eliminating their footprints. Follower devices only ever need a resistor connected to MSEL2 to program their stack phase position and current limit selection.
JH,
I reviewed the compensation, and believe Pin Programmed Compensation Code 14 would be good for a 4-phase design with 20x 100μF + 16x 220μF at 550kHz switching frequency. That would require MSEL1_A on device 1 to be connected to its AGND with 14.7kΩ (R111)
Pin Programming:
Device 1, Rail A
MSEL1: 14.7kΩ (R111)
MSEL2: 8.25kΩ (R113)
VSEL: 17.8kΩ (R107)
ADRSEL: I don't see a target PMBus address, so I can't recommend a resistor value, but I would recommend programming the SYNC state for SYNC_OUT with a top-side resistor to BP1V5_A (R109 / R108)
Device 1, Rail B
MSEL2: 68.1kΩ (R121)
Device 2, Rail A
MSEL2: 6.81kΩ (R92)
Device 2, Rail B
MSEL2: 31.6kΩ (R105)
Hello Peter,
Thanks for your kind reply.
The customer has additional questions.
1. Are there any performance results for current variation with temperature for 4-phase application?
2. If you have a layout guide for 4-phase application, please share.
3. How is the load sharing for the 4 output ports done in a 4 phase application of the TPSM8D6C24?
When there is an actual 80A load out of 140A, does 20A load on each output port? Or could it take more load on certain ports?
Regards,
JH
1. Are there any performance results for current variation with temperature for 4-phase application?
I am not sure I understand the question
2. If you have a layout guide for 4-phase application, please share.
I do not have a specific 4-phase layout guideline. The most sensitive module to module connection is the VSHARE pin, which drive the regulation and current share function. It should be kept away from noisy signals and shielded from SYNC by a ground trace. The ground trace should be connected to the ground plane at least once every 12mm
Best current sharing is achieves when the direction of current flow is perpendicular to the line between the modules. When current is drawn in-line with the line between the modules, the mutual current flowing in the ground between the more distant module and the load will create a ground differential between the modules, which will induce a current share error.
3. How is the load sharing for the 4 output ports done in a 4 phase application of the TPSM8D6C24?
When there is an actual 80A load out of 140A, does 20A load on each output port? Or could it take more load on certain ports?
The current sharing is very accurate, within 10%. For an 80A load, the individual phases will be between 18A and 22A. The Average Current Mode Control topology also ensures that phases will share current during a load transient.