• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 2 answers
  • Subscribers 64 subscribers
  • Views 251 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISO5852S-EP: Regarding READY AND FAULT SIGNALS

Vivek Gandham
Prodigy 180 points
Part Number: ISO5852S-EP

Hi Team,

Hope you are doing well,

I am Vivek Gandham, I am using the mentioned  06 Isolated gate drivers in my application. In this Gate driver Ready and Fault signals are given to GPIO's, Due to less GPIO's in my processor, I am not able to assign seperate GPIO's to them. Can I connect them to gate logic's and connect to processor with single GPIO. Is the Fault and Ready signals of gate driver will always high when the I/P is given to them or there any conditions to be considered? Please guide with this situation...

Thanks and Regards 

Vivek Gandham

  • 0
    TI__Expert 7080 points

    Hi Vivek,

    Thanks for your interest in ISO5852,

    RDY and nFLT are open-drain pins, both can be tied together and then connected with 5K ohm resistor to the CPU's GPIO. By default, if no fault and the device is powered , both pins will be high. During FLT/Power supplies going below UVLO, the corresponding pin will be pulled down. Only down side is, it can not be differentiated which pin is pulling down.

    If this answers your question, please press the "Green" button.

    Thanks and Regards,

    Sasi, 

    Applications – Isolated High Power Drivers

  • 0 in reply to Sasikala Thangam
    TI__Expert 7080 points

    One small correction: 5K ohms is the pull up resistor, the nFLT and Ready pins to be connected to 5K resistor to VCC. and can be connected to the GPIO.