TPS2663: How to use VPGTHR

Hi, Rakesh

Thank you for your replay.

What are the conditions for Gate Enhanced (HS_FET) to go high?

Best regards,

Watanbe

Thanks Rakesh

Please let me know the following three questions.

(1)Which part of the block diagram does the GATE mentioned above refer to?

(2)In the above block diagram, when PGTH > 1.2V, the output of the hysteresis comparator for PGTH goes low and PGOOD does not go high?

(3)When the SHDN terminal is open, is the input terminal R of the RS flip-flop always low?
As a result of checking our system, PGOOD becomes Low when SHDN=OPEN and PGTH falls below the threshold.
In the block diagram, it seems that PGOOD will never go low if R is always low, so the behavior does not match.

Best regards, Watanabe

Hi Watanbe,

1A) GATE of the internal FET

2A) You are right, the polarity of the PGTH comparator should be reversed.

3A) We will check on this and get back to you.

Best Regards,

Rakesh

Thanks Rakesh

1A) Could you tell me the conditions under which the GATE of the internal FET crosses VIN+3V in the gate control logic?

2A) What is the mean of your comment"the polarity of the PGTH comparator should be reversed" ?
Is it the output of the PGTH comparator? or input?

3A) OK.

Best regards, Watanabe

Hi Watanbe,

1A) when SWEN is HIGH

2A)

3A) When SHDNb is Open, it is pulled high internally, then PGTH pin will decide the state of PGOOD output. If PGTH is low, PGOOD Is low and it PGTH is high, PGOOD is high. So, OR gate is correct for SHDNb and PGTH signals.

Hi Rakesh,

1A) I think SWEN goes high when Vout reaches Vin (Vin_sys) during startup, but in the block diagram, the output of the comparator is reversed, so it goes high before Vout reaches Vin (Vin_sys). Are my thoughts correct?

2A) I understood. thank you.

3A) If SHDN is open and internally pulled up to 2.7V, SHDNb will always be high, so the OR gate output will always be high regardless of the state of PGTH. Is the SHDNb of the OR gate input reversed? Or is the polarity of the comparator that outputs SHDNb reversed?

Best regards, Watanabe

Let me check and get back to you!

Hi Watanbe,

1A) It is correct. When IN_SYS is higher that +ve input of comparator, the output of comparator is 0 which then negates before going to AND gate

2A) OK

3A) Got what you are saying.. the SHDNb should be a negate. Now, it make sense.

Best regards, Rakesh

Hi Rakesh,

Thank you for your reply.

1A) Is it only in the reverse connection that the above comparator output becomes 1 and is negated before proceeding to the AND gate?
In that case, I think PGOOD goes high at the same time as Vout starts rising at startup.However, in Figure 21 of the datasheet and in our system, PGOOD is high when Vin = Vout at startup, so I think it doesn't match the block diagram.

3A)I understood.Thank you.

Best regards, Watanabe

Hi Watanbe,

Is it only in the reverse connection that the above comparator output becomes 1 and is negated before proceeding to the AND gate?

Rakesh-> yes

Our designer confirmed that the power good block mentioned above is correct. Can you explain step-by-step where it is not matching.